JG82852GMSL7VP Datasheet, PDF (125/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Functional Description
R
Presence Detect port on the SO-DIMMs via a series of I/O cycles to the south bridge. The BIOS needs
to determine the size and type of System Memory used for each of the rows of System Memory in order
to properly configure the GMCH System Memory interface.
For SMBus Configuration and Access of the Serial Presence Detect Ports, refer to the Intel 82801DBM
I/O Controller Hub 4 Mobile (ICH4-M) Datasheet (order number: 252337) for more detail.
5.3.2.2. System Memory Register Programming
This section provides an overview of how the required information for programming the DDR SDRAM
registers is obtained from the Serial Presence Detect ports on the SO-DIMMs. The Serial Presence
Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by
row basis), DDR SDRAM Timings, Row Sizes and Row Page Sizes. The following table lists a subset
of the data available through the on board Serial Presence Detect ROM on each SO-DIMM.
Table 27. Data Bytes on SO-DIMM Used for Programming DRAM Registers
Byte
Function
2
System Memory Type (DDR SDRAM)
3
Number of Row Addresses, not counting Bank Addresses
4
Number of Column Addresses
5
Number of SO-DIMM banks
11
No ECC
12
Refresh Rate/Type
17
Number Banks on each Device
The above table is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively
provide enough data for programming the GMCH DDR SDRAM registers.
5.3.3.
DDR SDRAM Performance Description
The overall System Memory performance is controlled by the DDR SDRAM timing register, pipelining
depth used in GMCH, System Memory speed grade and the type of DDR SDRAM used in the system.
Besides this, the exact performance in a system is also dependent on the total System Memory
supported, external buffering and System Memory array layout. The most important contribution to
overall performance by the System Memory controller is to minimize the latency required to initiate and
complete requests to System Memory, and to support the highest possible bandwidth (full streaming,
quick turn-arounds). One measure of performance is the total flight time to complete a cache line
request. A true discussion of performance really involves the entire chipset, not just the System Memory
controller.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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