JG82852GMSL7VP Datasheet, PDF (105/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.11.6.
CC – Class Code Register - Device #2
Address Offset:
Default Value:
Access:
Size:
09h 0Bh
030000h
Read Only
24 bits
This register contains the device programming interface information related to the Sub-Class Code and
Base Class Code definition for the IGD. This register also contains the Base Class Code and the function
sub-class in relation to the Base Class Code.
Bit
23:16
15:8
7:0
Description
Base Class Code (BASEC): 03=Display controller
Sub-Class Code (SCC):
Function 0: 00h=VGA compatible or 80h=Non VGA
Function 1: 80h=Non VGA
Programming Interface (PI): 00h=Hardwired as a Display controller.
3.11.7.
CLS – Cache Line Size Register - Device #2
Address Offset:
Default Value:
Access:
Size:
0Ch
00h
Read only
8 bits
The IGD does not support this register as a PCI slave.
Bit
7:0 Cache Line Size (CLS) – RO
Description
3.11.8.
MLT2 – Master Latency Timer Register - Device #2
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read Only
8 bits
The IGD does not support the programmability of the master latency timer because it does not perform
bursts.
Bit Description
7:0 Master Latency Timer Count Value – RO
Intel^® 852GM/852GMV Chipset GMCH Datasheet
105