JG82852GMSL7VP Datasheet, PDF (69/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.19.
SMRAM – System Management RAM Ctrl Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
60h
02h
Read/Write/Lock, Read Only
8 bits
The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated.
The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the Open bit
must be reset before the LOCK bit is set.
Bit
7
6
5
4
3
2:0
Description
Reserved
SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the SMM space DDR SDRAM is made
visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software
should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK is set to a 1,
D_OPEN is reset to 0 and becomes read only.
SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DDR SDRAM is not accessible to data
references, even if SMM decode is active. Code references may still access SMM space DDR SDRAM.
This will allow SMM software to reference “through” SMM space to update the display even when SMM is
mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the
same time. D_CLS applies to all SMM spaces (Cseg, Hseg, and Tseg).
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN,
G_SMRAME, C_BASE_SEG, GMS, DRB, DRA, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read
only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset.
The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to “lock down” SMM space in the future so
that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has
knowledge of the D_OPEN function.
Global SMRAM Enable (G_SMRAME): If set to a 1, then Compatible SMRAM functions is enabled,
providing 128 kB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To
enable Extended SMRAM function this bit has be set to 1. Refer to the section on SMM for more details.
Once D_LCK is set, this bit becomes read only.
Compatible SMM Space Base Segment (C_BASE_SEG)—RO: This field indicates the location of SMM
space. “SMM DRAM” is not remapped. It is simply “made visible” if the conditions are right to access SMM
space, otherwise the access is forwarded to Hub Interface. C_BASE_SEG is hardwired to 010 to indicate
that the Intel 852GM/852GMV GMCH supports the SMM space at A0000h–BFFFFh.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
69