JG82852GMSL7VP Datasheet, PDF (149/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Testability
R
7.2. XOR Chain Differential Pairs
Table 31 provides differential signals in the XOR chains that must be treated as pairs. Pin1 and Pin2 as
shown below need to drive to the opposite value always.
Table 31. Differential Signals in the XOR Chains
Pin1
Pin2
XOR Chain
DVOCCLK#
HLSTB#
DVOCCLK
HLSTB
DVO XOR 2
HUB XOR
7.3. XOR Chain Exclusion List
See Table 32 for a list of pins that are not included in the XOR chains (excluding all VCC/VSS/VTT).
Note: Connectivity column is used to identify what need to be driven on that particular pin during XOR chain
test mode.
Table 32. XOR Chain Exclusion List of Pins
Item#
IN/OUT
Ball
Pin/VHDL
I/O Type
Voltage
Connectivity
1
IN
Y3
GCLKIN
PLL CLK
3.3
0
2
-
W1
HLVREF
Analog
1/3 VCCHL
0.4
3
-
T2
HLRCOMP
Analog
N/A
N/A
4
-
U2
PSWING
Analog
N/A
N/A
5
-
F1
GVREF
Analog
1/2 VCCDVO
0.75
6
-
D1
DVORCOMP
Analog
N/A
N/A
7
IN
J11
PWROK
CMOS
3.3
N/A
8
IN
B7
DREFCLK
PLL CLK
3.3
0
9
-
E8
REFSET
Analog
N/A
N/A
10
-
C9
BLUE
Analog
N/A
N/A
11
-
D9
BLUE#
Analog
N/A
N/A
12
-
C8
GREEN
Analog
N/A
N/A
13
-
D8
GREEN#
Analog
N/A
N/A
14
A7
RED
Analog
N/A
N/A
15
-
A8
RED#
Analog
N/A
N/A
16
-
D12
LVREFH
Analog
1.1
1.1
17
-
A10
LIBG
Analog
N/A
N/A
18
-
B12
LVBG
Analog
N/A
N/A
19
-
F12
LVREFL
Analog
1.1
1.1
20
IN
B17
DREFSSCLK
PLL CLK
3.3
0
21
-
J17
HDVREF[2]
Analog
2/3 VTTLF
1.0
Intel^® 852GM/852GMV Chipset GMCH Datasheet
149