JG82852GMSL7VP Datasheet, PDF (65/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.18.
PAM(6:0) – Programmable Attribute Map Register (Device 0)
Address Offset:
Default Value:
Attribute:
Size:
59–5Fh
00h Each
Read/Write
4 bits/register, 14 registers
The Intel 852GM/852GMV GMCH allows programmable DDR SDRAM attributes on 13 Legacy
System Memory segments of various sizes in the 640 kB –1 MB address range. Seven Programmable
Attribute Map (PAM) Registers are used to support these features. Cacheability of these areas is
controlled via the MTRR registers in the P6 processor. Two bits are used to specify System Memory
attributes for each System Memory segment. These bits apply to both host and Hub Interface initiator
accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding System Memory
segment are claimed by the Intel 852GM/852GMV GMCH and directed to main System Memory.
Conversely, when RE = 0, the host read accesses are directed to PCI0.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding System Memory
segment are claimed by the Intel 852GM/852GMV GMCH and directed to main System Memory.
Conversely, when WE = 0, the host write accesses are directed to PCI0.
The RE and WE attributes permit a System Memory segment to be Read Only, Write Only, Read/Write,
or disabled. For example, if a System Memory segment has RE = 1 and WE = 0, the segment is Read
Only.
Each PAM Register controls two regions, typically 16 kB in size. Each of these regions has a 4-bit field.
The four bits that control each region have the same encoding and are defined in the following table.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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