JG82852GMSL7VP Datasheet, PDF (46/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.2. Nomenclature for Access Attributes
Table 13 provides the nomenclature for the access attributes.
Table 13. Nomenclature for Access Attributes
RO
Read Only. If a register is read only, writes to this register have no effect.
R/W
Read/Write. A register with this attribute can be read and written.
R/W/L
Read/Write/Lock. A register with this attribute can be read, written, and Lock.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a
write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
R/WO
Read/Write Once. A register bit with this attribute can be written to only once after power
up. After the first write, the bit becomes read only.
L
Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
Reserved Bits
Some of the GMCH registers described in this section contain reserved bits. These bits are
labeled "Reserved”. Software must deal correctly with fields that are reserved. On reads,
software must use appropriate masks to extract the defined bits and not rely on reserved
bits being any particular value. On writes, software must ensure that the values of reserved
bit positions are preserved. That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written back. Note the software
does not need to perform read, merge, and write operation for the Configuration Address
register.
Reserved Registers
In addition to reserved bits within a register, the GMCH contains address locations in the
configuration space of the Host-Hub Interface Bridge entity that are marked either
"Reserved" or “Intel Reserved”. The GMCH responds to accesses to “Reserved” address
locations by completing the host cycle. When a “Reserved” register location is read, a zero
value is returned. (“Reserved” registers can be 8-bit, 16-bit, or 32-bit in size). Writes to
“Reserved” registers have no effect on the GMCH. Registers that are marked as “Intel
Reserved” must not be modified by system software. Writes to “Intel Reserved” registers
may cause system failure. Reads to “Intel Reserved” registers may return a non-zero
value.
Default Value upon a
Reset
Upon Reset, the GMCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping options.
The default state represents the minimum functionality feature set required to successfully
bringing up the system. Hence, it does not represent the optimal system configuration. It is
the responsibility of the system initialization software (usually BIOS) to properly determine
the DRAM configurations, operating parameters and optional system features that are
applicable, and to program the GMCH registers accordingly.
S
SW Semaphore.
A physical PCI bus #0 does not exist. The Hub Interface and the internal devices in the GMCH and
ICH4-M logically constitute PCI Bus #0 to configuration software.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet