JG82852GMSL7VP Datasheet, PDF (72/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.22.
ERRCMD – Error Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
64–65h
0000h
Read/Write
16 bits
This register enables various errors to generate a SERR Hub Interface special cycle. Since the Intel
852GM/852GMV GMCH does not have a SERR# signal, SERR messages are passed from the Intel
852GM/852GMV GMCH to the ICH4-M over Hub Interface. The actual generation of the SERR
message is globally enabled for Device #0 via the PCI Command register.
Note: An error can generate one and only one Hub Interface error special cycle. It is software’s responsibility
to make sure that when an SERR error message is enabled for an error condition, SMI and SCI error
messages are disabled for that same error condition.
Bit
15:14
13
12
11
10
9
8
7
6
Description
Reserved
SERR on FSB Strobe Glitch : When this bit is asserted, the Intel 852GM/852GMV GMCH will generate a HI
SERR message when a glitch is detected on one of the FSB Strobes.
Reserved
SERR on Intel 852GM/852GMV GMCH Thermal Sensor Event:
1 = The Intel 852GM/852GMV GMCH generates a SERR Hub Interface special cycle on a thermal sensor
trip that requires an SERR. The SERR must not be enabled at the same time as the SMI/SCI for a
thermal sensor trip event.
0 = Software must write a 1 to clear this status bit.
Reserved
SERR on LOCK to non-DDR SDRAM Memory:
1 = The Intel 852GM/852GMV GMCH generates an SERR Hub Interface special cycle when a CPU initiated
LOCK transaction targeting non-DDR SDRAM memory space occurs.
0 = Disable. Reporting of this condition is disabled.
SERR on DDR SDRAM Refresh timeout:
1 = The Intel 852GM/852GMV GMCH generates an SERR Hub Interface special cycle when a DDR SDRAM
Refresh timeout occurs.
0 = Disable. Reporting of this condition is disabled.
SERR on DDR SDRAM Throttle Condition:
1 = The Intel 852GM/852GMV GMCH generates an SERR Hub Interface special cycle when a DDR SDRAM
Read or Write Throttle condition occurs.
0 = Disable. Reporting of this condition is disabled.
SERR on Receiving Target Abort on Hub Interface:
1 = The Intel 852GM/852GMV GMCH generates an SERR Hub Interface special cycle when an Intel
852GM/852GMV GMCH originated Hub Interface cycle is terminated with a Target Abort.
0 = Disable. Reporting of this condition is disabled.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet