JG82852GMSL7VP Datasheet, PDF (89/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
Bit
Description
written to a value different than “000”. On this event, all CKE signals are asserted.
During suspend (S3, S4), Intel 852GM/852GMV GMCH internal signal triggers DDR SDRAM controller to
flush pending commands and enter all rows into Self-Refresh mode. As part of resume sequence, Intel
852GM/852GMV GMCH will be reset – which will clear this bit field to “000” and maintain CKE signals
deasserted. After internal reset is deasserted, CKE signals remain deasserted until this field is written to a
value different than “000”. On this event, all CKE signals are asserted.
During entry to other low power states (C3, S1-M), Intel 852GM/852GMV GMCH internal signal triggers DDR
SDRAM controller to flush pending commands and enter all rows in S1 and relevant rows in C3 (Based on
RPDNC3) into Self-Refresh mode. During exit to normal mode, the GMCH signal triggers DDR SDRAM
controller to exit Self-Refresh and resume normal operation without S/W involvement.
001: NOP Command Enable – All CPU cycles to DDR SDRAM result in a NOP command on the DDR
SDRAM interface.
010: All Banks Pre-charge Enable – All CPU cycles to DDR SDRAM result in an “all banks precharge”
command on the DDR SDRAM interface.
011: Mode Register Set Enable – All CPU cycles to DDR SDRAM result in a “mode register” set command
on the DDR SDRAM interface. Host address lines are mapped to DDR SDRAM address lines in order to
specify the command sent. Host address HA[13:3] are mapped to memory address MA[11, 9:0]. MA3 must
be driven to 1 for interleave wrap type.
For Double Data Rate
MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field.
CAS Latency MA[6:4]
1.5 Clocks
001
2.0 Clocks
010
2.5 Clocks
110
MA[7] should always be driven to a 0.
MA[8] Should be driven to a 1 for DLL Reset and 1 for Normal Operation.
MA[12:9] must be driven to 00000.
BIOS must calculate and drive the correct host address for each row of memory such that the correct
command is driven on the MA[12:0] lines. Note that MAB[7:4]# are inverted from MAA[7:4]; BIOS must
account for this.
100: Extended Mode Register Set Enable – All CPU cycles to DDR SDRAM result in an “extended mode
register set” command on the DDR SDRAM interface. Host address lines are mapped to DDR SDRAM
address lines in order to specify the command sent. Host address lines are mapped to DDR SDRAM address
lines in order to specify the command sent. Host address HA[13:3] are mapped to memory address [9:0].
MA[0] = 0 for DLL enable and 1 for DLL disable. All the other MA lines are driven to 0s. Note that MAB[7:4]#
are inverted from MAA[7:4]; BIOS must account for this.
101: Reserved
110: CBR Refresh Enable – In this mode all CPU cycles to DDR SDRAM result in a CBR cycle on the DDR
SDRAM interface
111: Normal operation
3:0
Reserved
Intel^® 852GM/852GMV Chipset GMCH Datasheet
89