JG82852GMSL7VP Datasheet, PDF (61/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.13.
RRBAR – Register Range Base Address Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
48 4Bh
00000000h
Read/Write, Read Only
32 bits
This register requests a 64-kB allocation for the Device registers. The base address is defined by bits 31
to 16 and can be used to access device configuration registers. Only Dword aligned writes are allowed to
this space. See the table below for address map within the 64-kB space. This addressing mechanism may
be used to write to registers that modify the device address map (includes all the BARs, PAMs, SMM
registers, Pre-Allocated System Memory registers etc). However, before using or allowing the use of the
modified address map the bios must synchronize using an IO or Read cycle.
Note: The GTLB cannot be enabled/disabled using this mechanism.
Bit
31:16
15:0
Description
Memory Base Address—R/W: Set by the OS, these bits correspond to address signals [31:16].
Reserved
Address Range
0000h to FFFFh
Space
Sub Ranges
0000h to 00FFh
0100h to 01FFh
0200h to 02FFh
0300h to 03FFh
0400h to 07FFh
0800h to 08FFh
0900h to 0FFFh
1000h to 10FFh
1100h to 11FFh
1200h to 7FFFh
8000h to 8FFFh
9000h to FFFFh
Description
Read/Write (As in Configuration Space): Maps to 00–FFh
of Device 0, Function 0 register space.
Read/Write (As in Configuration Space): Maps to 00–FFh
of Device 0, Function 1 register space.
Reserved
Read/Write (As in Configuration Space): Maps to 00–FFh
of Device 0, Function 3 register space.
Reserved
Read/Write (As in Configuration Space): Maps to 00–FFh
of Device 1, Function 0 register space.
Reserved
Read/Write (As in Configuration Space): Maps to 00–FFh
of Device 2, Function 0 register space.
Read/Write (As in Configuration Space): Maps to 00–FFh
of Device 2, Function 1 register space.
Reserved
System Memory RCOMP memory Range.
Reserved
Intel^® 852GM/852GMV Chipset GMCH Datasheet
61