JG82852GMSL7VP Datasheet, PDF (74/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.23.
SMICMD – SMI Error Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
66h
00h
Read/Write
8 bits
This register enables various errors to generate an SMI Hub Interface special cycle. When an error flag is
set in the ERRSTS register it can generate a SERR, SMI, or SCI Hub Interface special cycle when
enabled in the ERRCMD, SMICMD, or SCICMD registers respectively.
Note: An error can generate one and only one Hub Interface error special cycle. It is software’s responsibility
to make sure that when an SMI error message is enabled for an error condition, SERR and SCI error
messages are disabled for that same error condition.
Bit
7:4
3
2
1
0
Description
Reserved
SMI on Intel 852GM/852GMV GMCH Thermal Sensor Trip:
1 = An SMI Hub Interface special cycle is generated by Intel 852GM/852GMV GMCH when the thermal sensor
trip requires an SMI. A thermal sensor trip point cannot generate more than one special cycle.
Reserved
SMI on Multiple-bit ECC Error:
1 = Reserved
0 = For systems that do not support ECC, this field must be set to 0(Intel 852GM/852GMV GMCH only).
SMI on Single-bit ECC Error:
1 = Reserved
0 = For systems that do not support ECC, this field must be set to 0 (Intel 852GM/852GMV GMCH only).
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Intel^® 852GM/852GMV Chipset GMCH Datasheet