JG82852GMSL7VP Datasheet, PDF (163/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Intel 852GM/852GMV GMCH Strap Pins
R
8. Intel 852GM/852GMV GMCH Strap
Pins
8.1. Strapping Configuration
Table 35. Strapping Signals and Configuration
Pin Name
Strap Description
Configuration
I/F Type
Buffer Type
HSYNC
VSYNC
LCLKCTLB
DVODETECT
GST[1]
GST[0]
*
XOR Chain Test
Low = Normal Ops (Default)
High = XOR Test On
GPIO
OUT
ALL Z Test
Low = Normal Ops (Default)
High = AllZ Test On
GPIO
OUT
VTT Voltage Select
High = Mobile Intel Pentium 4
Processor–M/ Mobile Intel
Celeron processor/Intel
Celeron M processor/Intel
Celeron D processor on 90 nm
process and in the 478-pin
package
GPIO
OUT
*DVO Select (If
DVODETECT=0 during
Reset, ADDID[7:0] is
latched to the ADDID
Register)
Low = DVO (Default)
High = Reserved
DVO
BI
* Clock Config: Bit_1
* Clock Config: Bit_0
Please refer to Device #0
Function #3 (HPLLCC
Register) for proper GST[1:0]
settings
DVO
Out:
0) Before
CPURST#, there
is internal pull-
down
1) Just out of
CPURST#:
These pins are
Hi-Z
2) C3: these
pins are Hi-Z
3) S1-M: these
pins are Hi-Z
4) Internal GFX
D1/D3: these
pins are Hi-Z
5) S3: these pins
are Power down
6) S4/S5: these
pins are Power
down
External pull-ups/downs will be required on the board to enable the non-default state of the straps.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
163