JG82852GMSL7VP Datasheet, PDF (11/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

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Intel^® 852GM Chipset GMCH Product Features
ƒ ^{Processor/Host Bus Support}
SDRAM (without ECC)
Intel^® Celeron^® processor (478-pin
Supports 128-Mbit, 256-Mbit, and 512-
package)
Mbit technologies providing maximum
Supports the processor subset of the
capacity of 1-GB with x16 devices and up
Enhanced Mode Scalable bus
to 2-GB with high density 512-Mbit
protocol 2X Address, 4X data
technology
Intel Celeron processor System Bus
All supported devices have 4 banks
interrupt delivery
Supports up to 16 simultaneous open pages
Mobile Intel^® Pentium^® 4 Processor-M
Supports page sizes of 2-kB, 4-kB, 8-kB,
(478-pin package)
and 16-kB. Page size is individually
Supports the subset of the Enhanced
selected for every row (UMA support only)
Mode Scalable bus protocol
ƒ ^{System Interrupts}
Mobile Intel Pentium 4 Processor-M
Supports Intel 8259 and FSB interrupt
System Bus interrupt delivery
delivery mechanism
Supports system bus at 400-MHz or
Supports interrupts signaled as upstream
3.2 GB/s
Memory Writes from PCI and Hub
Supports host Dynamic Bus
Interface
Inversion (DBI)
MSI sent to the CPU through the System
Supports 32-bit host bus addressing
Bus
12-deep In-Order-Queue
ƒ ^{Internal Graphics Features}
AGTL+ bus driver technology with
Up to 64-MB of Dynamic Video Memory
integrated AGTL termination
Allocation
resistors
Supports Enhanced Intel SpeedStep^®
Display Image Rotation
Core Frequency
technology
Intel^® Celeron^® M processor
Display Core frequency of 133-MHz
Render Core frequency of 133-MHz
400-MHz front side bus frequency.
2D Graphics Engine
Source synchronous double pumped
Optimized 128-bit BLT engine
address (2X)
Ten programmable and predefined
Source synchronous quad pumped
monochrome patterns
data (4X)
Alpha Stretch Blt (via 3D pipeline)
FSB interrupt delivery
Anti-aliased lines
Supports Host bus dynamic bus
inversion (DBI)
Hardware-based BLT Clipping and
Scissoring
Supports 32-bit host bus addressing
32-bit Alpha Blended cursor
8-deep in-order queue
Programmable 64 x 64 3-color
AGTL+ bus driver technology with
Transparent cursor
integrated AGTL+ termination
resistors
ƒ ^{Memory System}
Color Space Conversion
3 Operand Raster BLTs
8-bit, 16-bit, and 32-bit color
Directly supports one DDR SDRAM
channel, 64-bits wide
Supports 200/266-MHz DDR SDRAM
devices with max of 2 Double-Sided SO-
DIMMs (4 rows populated) with
unbuffered PC1600/PC2100 DDR
Triangle Lists, Strips and Fans
support
ROP support
DIB translation and Linear/Tile
addressing
3D Graphics Engine
3D Setup and Render Engine
Viewpoint Transform and Perspective
Divide
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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