JG82852GMSL7VP Datasheet, PDF (78/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.9.3.
PCICMD – PCI Command Register
Address Offset:
Default Value:
Access:
Size:
04h
0006h
Read Only, Read/Write
16 bits
Since Intel 852GM/852GMV Chipset Device #0 does not physically reside on PCI_A, many of the bits
are not implemented.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Descriptions
Reserved
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back
write. Since Device #0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this
bit position have no affect.
Default Value= 0
SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the Intel
852GM/852GMV GMCH and this bit is hardwired to 0. Writes to this bit position have no effect.
Default Value = 0
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the Intel
852GM/852GMV GMCH, and this bit is hardwired to 0. Writes to this bit position have no effect.
Default Value = 0
Parity Error Enable (PERRE): PERR# is not implemented by Intel 852GM/852GMV GMCH and this bit
is hardwired to 0. Writes to this bit position have no effect.
Default Value = 0
VGA Palette Snoop Enable (VGASNOOP): The Intel 852GM/852GMV GMCH does not implement this
bit and it is hardwired to a 0. Writes to this bit position have no effect.
Default Value = 0
Memory Write and Invalidate Enable (MWIE): The Intel 852GM/852GMV GMCH will never issue
memory write and invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will
have no effect.
Default Value = 0
Special Cycle Enable (SCE): The Intel 852GM/852GMV GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
Default Value = 0
Bus Master Enable (BME): The Intel 852GM/852GMV GMCH is always enabled as a master on HI.
This bit is hardwired to a “1”. Writes to this bit position have no effect.
Default Value = 1
Memory Access Enable (MAE): The Intel 852GM/852GMV GMCH always allows access to main
System Memory. This bit is not implemented and is hardwired to 1. Writes to this bit position have no
effect.
Default Value = 1
I/O Access Enable (IOAE): This bit is not implemented in the Intel 852GM/852GMV GMCH and is
hardwired to a 0. Writes to this bit position have no effect.
Default Value = 0
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Intel^® 852GM/852GMV Chipset GMCH Datasheet