JG82852GMSL7VP Datasheet, PDF (58/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.8.7.
BCC – Base Class Code
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
Read Only
8 bits
This register contains the Base Class Code of the Intel 852GM/852GMV GMCH Device #0. This code is
06h indicating a Bridge device.
3.8.8.
Bit
7:0
Descriptions
Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the Intel
852GM/852GMV GMCH. This code has the value 06h, indicating a Bridge device.
HDR – Header Type
Address Offset:
Default Value:
Access:
Size:
0Eh
80h
Read Only
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
3.8.9.
Bit
7:0
Descriptions
PCI Header (HDR): This field always returns 80 to indicate that Device 0 is a multifunction device. If
Functions other than 0 are disabled this field returns a 00 to indicate that the Intel 852GM/852GMV GMCH is
a single function device with standard header layout. The default is 80; Writes to this location have no effect.
SVID – Subsystem Vendor Identification
Address Offset:
Default Value:
Access:
Size:
2Ch
0000h
Read/Write Once
16 bits
This value is used to identify the vendor of the subsystem.
Bit
15:0
Descriptions
Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the vendor of
the system board. After it has been written once, it becomes read only.
Default Value=0
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Intel^® 852GM/852GMV Chipset GMCH Datasheet