JG82852GMSL7VP Datasheet, PDF (35/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Signal Description
R
2.4. Clocks
Table 6. Clock Signals
Signal Name
Type
Host Processor Clocking
BCLK
BCLK#
I
CMOS
System Memory Clocking
SCK[5:0]
O
SSTL_2
SCK[5:0]#
O
SSTL_2
DVO/Hub Input Clocking
GCLKIN
I
CMOS
DVO Clocking
DVOCCLK
DVOCCLK#
O
DVO
DVOBCCLKINT
I
DVO
DPMS
I
DVO
DAC Clocking
Description
Differential Host Clock In: These pins receive a buffered host clock from the
external clock synthesizer. This clock is used by all of the GMCH logic that is in the
Host clock domain (host, Hub and System Memory). The clock is also the
reference clock for the graphics core PLL. This is a low voltage differential input.
Differential DDR Clock: SCK and SCK# pairs are differential clock outputs. The
crossing of the positive edge of SCK and the negative edge of SCK# is used to
sample the address and control signals on the DDR SDRAM. There are 3 pairs to
each SO-DIMM.
NOTE: ECC error detection is NOT supported: SCK[2], SCK[5] signals should be
left as NC (“No Connect”) on the Intel 852GM/852GMV GMCH.
Complementary Differential DDR Clock: These are the complimentary
differential DDR SDRAM clock signals.
NOTE: ECC error detection is NOT supported: SCK[2]#, SCK[5]# signals should
be left as NC (“No Connect”) on the Intel 852GM/852GMV GMCH.
Input Clock: 66-MHz, 3.3-V input clock from external buffer DVO/Hub Interface.
Differential DVO Clock Output: These pins provide a differential pair reference
clock that can run up to 165 MHz.
DVOCCLK corresponds to the primary clock out.
DVOCCLK# corresponds to the primary complementary clock out.
DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if the DVO C
port is not implemented.
DVOBC Pixel Clock Input/Interrupt: This signal may be selected as the reference
input to either dot clock PLL (DPLL) or may be configured as an interrupt input. A
TV-out device can provide the clock reference. The maximum input frequency for
this signal is 85 MHz.
DVOBC Pixel Clock Input: When selected as the dot clock PLL (DPLL) reference
input, this clock reference input supports SSC clocking for DVO LVDS devices.
DVOBC Interrupt: When configured as an interrupt input, this interrupt can support
for either of the DVOB or DVOC.
DVOBCCLKINT needs to be pulled down if the signal is NOT used.
Display Power Management Signaling: This signal is used only in mobile
systems to act as the DREFCLK in certain power management states(i.e. display
power down mode); DPMS Clock is used to refresh video during S1-M. Clock Chip
is powered down in S1-M. DPMS should come from a clock source that runs during
S1-M and needs to be 1.5 V. So, an example would be to use a 1.5-V version of
SUSCLK from ICH4-M.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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