JG82852GMSL7VP Datasheet, PDF (93/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
Bit
11
10
9
8
7:0
Description
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults to 0.
Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become read-only.
Thermal Throttle Lock (TTLOCK): This bit secures the DDR SDRAM throttling control register. This bit
defaults to 0. Once a 1 is written to this bit, all of the configuration register bits in DTC (including
TTLOCK) except CTLOCK, RCTC and WCTC become read-only.
Thermal Power Throttle Control fields Enable:
0 = RTTC and WTTC are not used. RCTC and WTCT are used for both counter and thermal based
throttling.
1 = RTTC and WTTC are used for thermal based throttling.
High Priority Stream Throttling Enable:
Normally High Priority Streams are not throttled when either the counter based mechanism or thermal
sensor mechanism demands throttling.
0 = Normal operation.
1 = Block High priority streams during throttling.
Global DDR SDRAM Sampling Window (GDSW): This 8-bit value is multiplied by 4 to define the length
of time in milliseconds (0–1020) over which the number of Octal Words (16 bytes) read/written is
counted and throttling is imposed. Note that programming this field to “00h” disables System Memory
throttling.
Recommended values are between 0.25 and 0.75 seconds.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
93