JG82852GMSL7VP Datasheet, PDF (140/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Functional Description
R
set to the common mode voltage. When in the send zeros state, the circuit is powered up but sends only
zero for the pixel color data regardless what the actual data is with the clock lines and timing signals
sending the normal clock and timing data.
5.5.2.4.
Single Channel versus Dual Channel Mode
Both single channel and dual channel modes are available to allow interfacing to either single or dual
channel panel interfaces. This LVDS port can operate in single channel or dual channel mode. Dual
channel mode uses twice the number of LVDS pairs and transfers the pixel data at twice the rate of the
single channel. In general, one channel will be used for even pixels and the other for odd pixel data.
The first pixel of the line is determined by the display enable going active and that pixel will be sent out
channel A. All horizontal timings for active, sync, and blank will be limited to be on two pixel
boundaries in the two channel modes.
5.5.2.5.
LVDS Channel Skew
When in dual channel mode, the two channels must meet the panel requirements with respect to the inter
channel skew.
5.5.2.6.
LVDS PLL
The Display PLL is used to synthesize the clocks that control transmission of the data across the LVDS
interface. The three operations that are controlled are the pixel rate, the load rate, and the IO shift rate.
These are synchronized to each other and have specific ratios based on single channel or dual channel
mode. If the pixel clock is considered the 1x rate, a 7x or 3.5x speed IO_shift clock needed for the high-
speed, serial outputs setting the data rate of the transmitters. The load clock will have either a 1x or .5x
ratio to the pixel clock.
5.5.2.7.
SSC Support
The GMCH is designed to tolerate 0.5%, 1.0%, and 2.5% down/center spread at a modulation rate from
30-50kHz triangle. An external SSC clock synthesizer can be used to provide the 48/66-MHz reference
clock into the GMCH Pipe B PLL.
5.5.2.8.
Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel power, the
backlight enable and the LVDS data timing delivery. In order to meet the panel power timing
specification requirements, two signals, PANELVDDEN and PANELBKLTEN are provided to control
the timing sequencing function of the panel and the backlight power supplies.
5.5.2.8.1.
Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the panel. The set of
timing parameters can vary from panel to panel vendor, provided that they stay within a predefined
range of values. The panel VDD power, the backlight on/off state and the LVDS clock and data lines
are all managed by an internal power sequencer.
A requested power-up sequence is only allowed to begin after the power cycle delay time requirement
T4 is met.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet