JG82852GMSL7VP Datasheet, PDF (19/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Introduction
R
1.
1.1.
Introduction
This document provides the design specifications for the Intel^® 852GM/GMVchipsets.
Terminology
Term
Description
BLI
Core
CPIS
CPU
DBI
DBL
DVO
DVI*
DVMT
EDID
Full Reset
GMCH
Hub Interface (HI)
Host
IGD
Intel 852GM/852GMV
GMCH
Intel 82801DBM ICH4-M
IPI
LFP
LVDS
MSI
Primary PCI
Back Light Inverter
The internal base logic in the Intel 852GM/852GMV GMCH
Common Panel Interface Specification
Central Processing Unit
Dynamic Bus inversion
Display Brightness Link
Digital Video Out
Digital Visual Interface is the interface specified by the DDWG (Digital Display Working
Group) DVI Spec. Rev. 1.0 utilizing only the Silicon Image developed T.M.D.S. protocol
Intel Dynamic Video Memory Technology
Extended Display Identification Data
A Full Intel 852GM/852GMV GMCH Reset is defined in this document when RSTIN# is
asserted
Graphics Memory Controller Hub
The proprietary interconnect between the Intel 852GM/852GMV GMCH and the
component. In this document, the Hub Interface cycles originating from or destined for
the ICH4-M are generally referred to as Hub Interface cycles. Hub cycles originating
from or destined for the primary PCI interface on are sometimes referred to as Hub
Interface/PCI cycles
This term is used synonymously with processor
Integrated Graphics Device
Refers to the GMCH component
The component contains the primary PCI interface, LPC interface, USB 2.0, ATA-100,
AC’97, and other I/O functions. It communicates with the Intel 852GM/852GMV GMCH
over a proprietary interconnect called the Hub Interface. Throughout this datasheet, the
Intel 82801DBM ICH4-M component will be referred to as the ICH4-M
Inter Processor Interrupt
Local Flat Panel
Low voltage differential signals used for interfacing to LCD panels
Message Signaled Interrupts. MSI allow a device to request interrupt service via a
standard memory write transaction instead of through a hardware signal
Physical PCI bus that is driven directly by the component. It supports only 5-V, 33-MHz
PCI or PCI0 2.2 compliant components. Communication between PCI0 and Intel
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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