JG82852GMSL7VP Datasheet, PDF (88/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.9.16.
DRC – DRAM Controller Mode Register - Device #0
Address Offset:
Default Value:
Access:
Size:
70-73h
00000081h
Read/Write, read-only
32 bits
Bit
31:30
29
28:24
23:22
21:20
19:16
15
14:10
9:7
6:4
Description
Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register
definition.
Initialization Complete (IC): This bit is used for communication of software state between the memory
controller and the BIOS. BIOS sets this bit to 1 after initialization of the DDR SDRAM memory array is
complete. Setting this bit to a “1” enables DDR SDRAM refreshes. On power up and S3 exit, the BIOS
initializes the DDR SDRAM array and sets this bit to a “1”. This bit works in combination with the RMS bits in
controlling refresh state:
IC Refresh State
0 OFF
1 ON
Reserved
Number of Channels (CHAN): Reflects that Intel 852GM/852GMV GMCH supports only one System
Memory channel.
00
One channel is populated appropriately
Others: Reserved
DDIM DDR SDRAM Data Integrity Mode:
No-ECC. No read-merge-write on partial writes. ECC data sense-amps are disabled and the data output is
tristate. (Default)
Reserved
RAS Lock-Out Enable: Set to a ‘1’ if all populated rows support RAS Lock-Out. Defaults to ‘0’.
If this bit is set to a ‘1’ the DDR SDRAM controller assumes that the DDR SDRAM guarantees tRAS min
before an auto precharge (AP) completes (Note that an AP is sent with a read or a write command). Also, the
DDR SDRAM controller does not issue an activate command to the auto pre-charged bank for tRP.
If this bit is set to a ‘0’ the DDR SDRAM controller does not schedule an AP if tRAS min is not met.
Reserved
Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what rate
refreshes will be executed.
000: Refresh disabled
001: Refresh enabled. Refresh interval 15.6 µsec
010: Refresh enabled. Refresh interval 7.8 µsec
011: Reserved.
111: Refresh enabled. Refresh interval 64 clocks (fast refresh mode)
Other: Reserved
Any change in the programming of this field resets the refresh counter to zero. This function is for testing
purposes, it allows test program to align refresh events with the test and thus improve failure repeatability.
Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM interface. The
special modes are intended for initialization at power up.
000: Post Reset state – When the Intel 852GM/852GMV GMCH exits reset (power-up or otherwise), the
mode select field is cleared to “000”. Software not expected to write this value, however if this value is
written there are no side effects (no self refresh or any other special DDR SDRAM cycle).
During any reset sequence, while power is applied and reset is active, the Intel 852GM/852GMV GMCH
deasserts all CKE signals. After internal reset is deasserted, CKE signals remain deasserted until this field is
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Intel^® 852GM/852GMV Chipset GMCH Datasheet