JG82852GMSL7VP Datasheet, PDF (101/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.11. Intel 852GM/852GMV GMCH Integrated Graphics
Device Registers (Device #2, Function #0)
This section contains the PCI configuration registers listed in order of ascending offset address. Device
#2 incorporates Function #0. See Section 3.2 for access nomenclature.
Table 22. Integrated Graphics Device Configuration Space (Device #2, Function#0)
Register Name
Register
Symbol
Address
Offset
Register
End
Default
Value
Access
Regs in
Function#1
Vendor Identification
VID2
00h
Device Identification
DID2
02h
PCI Command Register
PCICMD2
04h
PCI Status Register
PCISTS2
06h
Revision Identification
RID2
08h
Class Code
CC
09h
Cache Line Size Register
CLS
0Ch
Master Latency Timer
MLT2
0Dh
Header Type
HDR2
0Eh
Graphics Memory Range
GMADR
10h
Address
Memory Mapped Range
MMADR
14h
Address
IO Range Register
IOBAR
18h
Subsystem Vendor ID
SVID2
2Ch
Subsystem ID
SID2
2Eh
Video Bios ROM Base
ROMADR
30h
Address
Interrupt Line Register
INTRLINE
3Ch
Interrupt Pin Register
INTRPIN
3Dh
Minimum Grant Register
MINGNT
3Eh
Maximum Latency
MAXLAT
3Fh
Register
Mirror of GMCH Misc
MGMiscC
50h
Control
Power Management
PMCAP
D2h
Capabilities
Power Management
PMCS
D4h
Control
01h
8086h
RO
03h
3582h
RO
05h
0000h
RO,R/W
07h
0090h
RO
08h
01h
RO
0Bh
030000h
RO
0Ch
00h
RO
0Dh
00h
RO
0Eh
00h
RO
13h
00000008h
R/W,RO
C0F0
C0F0
U1F1
U1F1
C0F0
U1F1
C0F0
C0F0
C0F0
U1F1
17h
00000000h
R/W,RO
U1F1
1Bh
00000001h
R/W,RO
2Dh
0000h
R/WO
2Fh
0000h
R/ WO
33h
00000000h
RO
C0F0
C0F0
C0F0
3Ch
00h
R/W, RO in F
#1
3Dh
01h
RO, Reserved
In F#1
3Eh
00h
RO
C0F0
3Fh
00h
RO
C0F0
51h
---
D3h
0221h
RO
CODO
FO GMCH
Misc Control
Register
RO
COFO
D5h
0000h
R/W,RO
U1F1
Intel^® 852GM/852GMV Chipset GMCH Datasheet
101