JG82852GMSL7VP Datasheet, PDF (90/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.9.17.
DTC – DRAM Throttling Control Register (Device 0)
Offset Address:
Default Value:
Access:
Size:
A0–A3h
00000000h
Read/Write/Lock
32 bits
Throttling is independent for System Memory Banks, Intel 852GM/852GMV GMCH Writes, and
thermal sensor trips. Read and Write Bandwidth is measured independently for each Bank. If the number
of Octal -Words (16 bytes) read/written during the window defined below (Global DDR SDRAM
Sampling Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR SDRAM
throttling mechanism will be invoked to limit DDR SDRAM reads/writes to a lower bandwidth checked
over smaller time windows. The throttling will be active for the remainder of the current GDSW and for
the next GDSW after which it will return to non-throttling mode. The throttling mechanism accounts for
the actual bandwidth consumed during the sampling window, by reducing the allowed bandwidth within
the smaller throttling window based on the bandwidth consumed during the sampling period. Although
bandwidth from/to independent rows and Intel 852GM/852GMV GMCH write bandwidth is measured
independently, once tripped all transactions except high priority graphics reads are subject to throttling.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet