JG82852GMSL7VP Datasheet, PDF (48/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.5.
Register Definitions
The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O address
space, and they are as follows:
Control registers: I/O mapped into the CPU I/O space, which control access to PCI
configuration space via Configuration Mechanism #1 in the PCI 2.2 specification.
Internal configuration registers: residing within the GMCH, they are partitioned into two
logical device register sets (“logical” since they reside within the single physical device). The first
register set is dedicated to Host-HI Bridge functionality (i.e. DDR SDRAM configuration, other
chip-set operating parameters and optional features). The second register block is for the
integrated graphics functions.
Internal Memory Mapped configuration registers: residing in GMCH Device #0.
Internal Memory Mapped configuration registers and Legacy VGA registers: residing in the
GMCH Device #2 that controls the Integrated Graphics Controller.
The GMCH internal registers (I/O Mapped and Configuration registers) are accessible by the Host CPU.
The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of
CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte numeric fields use “little-
endian” ordering (i.e., lower addresses contain the least significant parts of the field).
Reserved Bits
Some of the GMCH registers described in this section contain reserved bits. These bits are labeled
“Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of
reserved bit positions must first be read, merged with the new values for other bit positions and then
written back.
Note: The software does not need to perform read, merge, and write operation for the configuration address
register.
Default Value upon Reset
Upon a full Reset, the GMCH sets all of its internal configuration registers to predetermined default
states. Some register values at reset are determined by external strapping options. The default state
represents the minimum functionality feature set required to successfully bring up the system. Hence, it
does not represent the optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DDR SDRAM configurations, operating parameters,
and optional system features that are applicable, and to program the GMCH registers accordingly.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet