JG82852GMSL7VP Datasheet, PDF (124/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Functional Description
5.2.2.
R
the address of the interrupt Memory Write. The GMCH forwards inbound Hub Interface Memory Writes
to address 0FEEx_xxxxh, to the System bus as “Interrupt Message Transactions”.
Upstream Interrupt Messages
The GMCH accepts message based interrupts from its Hub Interface and forwards them to the System
bus as Interrupt Message Transactions. The interrupt messages presented to the GMCH are in the form
of Memory Writes to address 0FEEx_xxxxh. At the Hub Interface the Memory Write interrupt message
is treated like any other Memory Write; it is either posted into the inbound data buffer (if space is
available) or retried (if data buffer space is not immediately available). Once posted, the Memory Write
from the Hub Interface, to address 0FEEx_xxxxh, is decoded as a cycle that needs to be propagated by
the GMCH to the System bus as an Interrupt Message Transaction.
5.3. System Memory Interface
5.3.1.
5.3.2.
5.3.2.1.
DDR SDRAM Interface Overview
The GMCH supports DDR SDRAM at 200/266-MHz and includes the following support:
Up to 1-GB of PC1600/PC2100 DDR SDRAM (Intel 852GM/852GMV GMCH)
PC1600/2100 unbuffered 200-pin DDR SDRAM SO-DIMMs
Maximum of two SO-DIMMs, single-sided and/or double-sided
The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH to support 64-
bit wide SO-DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology. While address
lines SMA[9:0] determine the starting address for a burst, burst length can only be 4. Four chip selects
SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM SO-DIMMs and four rows
of double-sided DDR SDRAM SO-DIMMs.
The GMCH main System Memory controller targets CAS latencies of 2 and 2.5 for DDR SDRAM. The
GMCH provides refresh functionality with a programmable rate (normal DDR SDRAM rate is 1
refresh/15.6 s). For write operations of less than a full cache line, GMCH will perform a cache-line
read and into the write buffer and perform byte-wise write-merging in the write buffer.
System Memory Organization and Configuration
Configuration Mechanism for SO-DIMMs
Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial Presence
Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification.
Before any cycles to the System Memory interface can be supported, the GMCH DDR SDRAM
registers must be initialized. The GMCH must be configured for operation with the installed System
Memory types. Detection of System Memory type and size is done via the System Management Bus
(SMB) interface on the ICH4-M. This two-wire bus is used to extract the DDR SDRAM type and size
information from the Serial Presence Detect port on the DDR SDRAM SO-DIMMs. DDR SDRAM SO-
DIMMs contain a 5-pin Serial Presence Detect interface, including SCL (serial clock), SDA (serial data)
and SA[2:0]. Devices on the SMBus have a 7-bit address. For the DDR SDRAM SO-DIMMs, the
upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA
are connected directly to the System Management Bus on the ICH4-M. Thus data is read from the Serial
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Intel^® 852GM/852GMV Chipset GMCH Datasheet