JG82852GMSL7VP Datasheet, PDF (26/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Introduction
1.7.3.
R
into a specific panel size as well as panning and centering support. The LVDS port is only supported on
Pipe B. The LVDS port can only be driven on Pipe B, either independently or simultaneously with the
DAC port.
Intel 852GM/852GMV GMCH Integrated DVO Port
The DVO C interface is compliant with the DVI Specification 1.0. When combined with a DVI
compliant external device (e.g. TMDS Flat Panel Transmitter, TV-out encoder, etc.), the GMCH
provides a high-speed interface to a digital or analog display (e.g. flat panel, TV monitor, etc.).
Intel 852GM/852GMV GMCH provides a DVO port that is capable of driving a 165-MHz pixel clock at
the DVO C interface. The DVO C port can be driven on Pipe A or Pipe B. If driven on port B, then the
LVDS port must be disabled.
1.8.
Hub Interface
A proprietary interconnect connects the GMCH to the ICH4-M Chipset. All communication between the
GMCH and the ICH4-M occurs over the Hub Interface. The Hub Interface runs at 66- MHz or 266-
MB/s.
1.9.
Address Decode Policies
Host initiated I/O cycles are positively decoded to the GMCH configuration space and subtractively
decoded to Hub Interface. Host initiated System Memory cycles are positively decoded to DDR
SDRAM and are again subtractively decoded to Hub Interface if under 4 GB. System Memory accesses
from Hub Interface to DDR SDRAM will be snooped on the FSB.
1.10.
Intel 852GM/852GMV GMCH Clocking
The GMCH has the following clock input/output pins:
400 MHz, Spread Spectrum, Low Voltage (1.3 V) Differential BCLK, BCLK# for Processor
System Bus
66-MHz Spread Spectrum, 3.3-V GCLKIN for Hub Interface buffers
Four pairs of differential output clocks (SCK[4,3,1:0], SCK[4,3,1:0]#), 200/266 MHz, 2.5 V for
System Memory interface
48-MHz, non-Spread Spectrum, 3.3-V DREFCLK for the Display Frequency Synthesis
48-MHz or 66-MHz, Spread Spectrum, 3.3-V DREFSSCLK for the Display Frequency Synthesis
Up to 85-MHz, 1.5-V DVOBCCLKINT for TV-Out mode
DPMS clock for S1-M
Clock Synthesizer chip(s) are responsible for generating the system host clocks, display and Hub
Interface clocks, PCI clocks, and System Memory clocks. The host target speed is 400 MHz. The
GMCH does not require any relationship between the BCLK host clock and the 66-MHz clock generated
for Hub Interface; they are asynchronous from each other. The Hub Interface runs at a constant 66-MHz
base frequency. Table 2 indicates the frequency ratios between the various interfaces that the GMCH
supports.
Please see Section 5.5.2.7 for details on the Intel 852GM/852GMV GMCH SSC Usage Model.
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Intel^® 852GM/852GMV Chipset GMCH Datasheet