JG82852GMSL7VP Datasheet, PDF (147/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Testability
R
7. Testability
In the Intel 852GM/852GMV GMCH, testability for Automated Test Equipment (ATE) board level
testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one
input pin connected to it. The XOR Chain test mode is used by product engineers during manufacturing
and OEMs during board level connectivity tests. The main purpose of this test mode is to detect
connectivity shorts between adjacent pins and to check proper bonding between I/O pads and I/O pins.
Figure 8. XOR–Tree Chain
VCC1_2
XOR
Out
7.1.
Input
Input
Input
Input
Input
xor.vsd
The algorithm used for in–circuit test is as follows:
1. Drive all input pins to an initial logic level 1. Observe the output corresponding to scan chain
being tested.
2. Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its
initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
XOR Test Mode Entry
Please refer to XOR Chain Test Mode Entry Events Diagram in Figure 9.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
147