JG82852GMSL7VP Datasheet, PDF (33/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Signal Description
R
2.2. DDR SDRAM Interface
Table 4. DDR SDRAM Interface Descriptions
Signal Name
Type
Description
SCS[3:0]#
SMA[12:0]
SBA[1:0]
SRAS#
SCAS#
SWE#
SDQ[71:0]
SDQS[8:0]
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_2
O
SSTL_
O
SSTL_2
I/O
SSTL_2
I/O
SSTL_2
Chip Select: These pins select the particular DDR SDRAM components during the
active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These
signals can be toggled on every rising System Memory Clock edge (SCMDCLK).
Multiplexed Memory Address: These signals are used to provide the multiplexed
row and column address to DDR SDRAM.
Bank Select (Memory Bank Address): These signals define which banks are
selected within each DDR SDRAM row. The SMA and SBA signals combine to
address every possible location within a DDR SDRAM device.
DDR Row Address Strobe: SRAS# may be heavily loaded and requires 2 DDR
SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and
SWE# (along with SCS#) to define the System Memory commands.
DDR Column Address Strobe: SCAS# may be heavily loaded and requires 2 DDR
clock cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE#
(along with SCS#) to define the System Memory commands.
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR
SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may
be heavily loaded and requires two DDR SDRAM clock cycles for setup time to the
DDR SDRAMs.
Data Lines: These signals are used to interface to the DDR SDRAM data bus.
NOTE: ECC error detection is NOT supported: SDQ[71:64] signals should be left as
NC (“No Connect”) on Intel 852GM/852GMV GMCH.
Data Strobes: Data strobes are used for capturing data. During writes, SDQS is
centered in data. During reads, SDQS is edge aligned with data. The following list
matches the data strobe with the data bytes.
There is an associated data strobe (DQS) for each data strobe (DQ) and check
bit (CB) group.
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
SDQS[5] -> SDQ[47:40]
SDQS[4] -> SDQ[39:32]
SDQS[3] -> SDQ[31:24]
SDQS[2] -> SDQ[23:16]
SDQS[1] -> SDQ[15:8]
SDQS[0] -> SDQ[7:0]
SCKE[3:0]
O
SSTL_2
NOTE: ECC error detection is NOT supported: SDQS[8] signal should be left as NC
(“No Connect”) on the Intel 852GM/852GMV GMCH.
Clock Enable: These pins are used to signal a self-refresh or power down command
to a DDR SDRAM array when entering system suspend. SCKE is also used to
dynamically power down inactive DDR SDRAM rows. There is one SCKE per DDR
SDRAM row. These signals can be toggled on every rising SCK edge.
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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