JG82852GMSL7VP Datasheet, PDF (83/176 Pages) Intel Corporation – Intel® 852GM/852GMV Chipset Intel® 852GM/852GMV Chipset Hub (GMCH)

Register Description
R
3.9.13.
DRA – DRAM Row Attribute Register - Device #0
Address Offset:
Default Value:
Access:
Size:
50-51h
77h Each
Read/Write
8 bits
The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing different
pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of rows:
Row0, 1:50h
Row2, 3:51h
52h-5Fh: Reserved.
76
R
Row attribute for Row1
4 32
R
0
Row Attribute for Row0
76
R
Row attribute for Row3
4 32
R
0
Row Attribute for Row2
Bit
Description
7
Reserved
6:4 Row Attribute for odd-numbered row: This field defines the page size of the corresponding row.
000: Reserved
001: 4 kB
010: 8 kB
011: 16 kB
111: Not Populated
Others: Reserved
3
Reserved
2:0 Row Attribute for even-numbered row: This field defines the page size of the corresponding row.
000: Reserved
001: 4 kB
010: 8 kB
011: 16 kB
111: Not Populated
Others: Reserved
Intel^® 852GM/852GMV Chipset GMCH Datasheet
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