DS537 Datasheet, PDF (95/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
By using the auto negotiation complete interrupt (see Interrupt Status Registers (IS0 and IS1), page 29 and
1000BASE-X Management Auto Negotiation Interrupt Control Register Table 71 on page 101.)
Loopback
There are two possible loopback positions:
• Loopback in the Hard TEMAC silicon component. When placed into loopback, data is routed from the
transmitter to the receiver path at the last possible point in the PCS/PMA sublayer. This is immediately before
the RocketIO transceiver interface. When placed into loopback, a constant stream of Idle code groups is
transmitted through the RocketIO transceiver. Loopback in this position allows test frames to be looped back
within the system without allowing them to be received by the link partner (the device connected on the other
end of the Ethernet. The transmission of Idles allows the link partner to remain in synchronization so that no
fault is reported.
• Loopback in the RocketIO transceiver. The RocketIO transceiver can be switched into loopback and will route
data from the transmitter path to the receiver path within the RocketIO transceiver. However, this data is also
transmitted out of the RocketIO transceiver and so any test frames used for a loopback test will be received by
the link partner.
Loopback can be enabled or disabled by writing to the 1000BASE-X Management Control Register bit 14 (Table 61
on page 96) while the loopback position can be controlled by writing the 1000BASE-X Management Loopback
Control Register bit 0 (Table 72 on page 101).
Internal 1000BASE-X PCS/PMA Management Registers
Registers 0 through 15 are defined in IEEE 802.3. These registers contain information relating to the operation of the
1000BASE-X PCS/PMA sublayer, including the status of the physical Ethernet link (PHY Link).
Additionally, these registers are directly involved in the operation of the 1000BASE-X auto negotiation function
which occurs between the XPS_LL_TEMAC and its link partner, the Ethernet device connected at the far end of the
PHY Link.
These registers are accessed via the MII Management interface (Using the MII Management to Access Internal or
External PHY Registers, page 67). These registers are only valid when using the 1000BASE-X PHY interface.
When using 1000BASE-X, the XPS_LL_TEMAC is typically connected to an external optical transceiver device such
as a GBIC or SFP transceiver.
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