DS537 Datasheet, PDF (65/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 43: Example of a Read and Clear of the TEMAC Interrupt Status Register
Register Access
Value
Activity
CTL0
Write
0x000003A0
Initiate the read from the Interrupt Status register by clearing the write enable and
providing the address for that indirectly addressed register
LSW0
Read
data word Read the current Interrupt Status register value
LSW0
Write
0x00000000
Write all zeros in preparation for transferring it to the Interrupt Status register thus
clearing all interrupts
CTL0
Write
0x000083A0
Initiate the write to the Interrupt Status register by setting the write enable and
providing the address for that indirectly addressed register
TEMAC Interrupt Enable (TIE) Registers
The TEMAC Interrupt Enable Register is shown in Figure 43. There is a separate register for each of the two
Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the address
used to access the LSW and CTL registers.
X-Ref Target - Figure 43
CfgWen
MiimWen
AfWen
FabrRen
25 26 27 28 29 30 31
Reserved
CfgRen
MiimRen
AfRen
DS537_43_091909
Figure 43: TEMAC Interrupt Enable Registers (ADDRESS_CODE 0x3A4)
Table 44 shows the TEMAC Interrupt Enable Registers bit definitions.
Table 44: TEMAC Interrupt Enable Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
31 FABR REN Read/Write
Fabric Read Interrupt Enable. This bit enables a completion interrupt for
a read access of a fabric register.
0
0 - no interrupt enabled
1 - interrupt enabled
MII Management Read Interrupt Enable. This bit enables completion
interrupt for a read access of a register using the MII management interface.
30
MIIM REN Read/Write
0
0 - no interrupt enabled
1 - interrupt enabled
MII Management Write Interrupt Enable. This bit enables completion
interrupt for a write access of a register using the MII management
29
MIIM WEN Read/Write
0
interface.
0 - no interrupt enabled
1 - interrupt enabled
Address Filter Read Interrupt Enable. This bit enables completion
interrupt for a read access of a multicast address table register.
28
AF REN Read/Write
0
0 - no interrupt enabled
1 - interrupt enabled
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