DS537 Datasheet, PDF (15/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 3: I/O Signal Description
Signal Name
Interface
Signal
Type
Init
Status
Description
ClientRxStatsByteVld_0
Statistics 0
O
0
TEMAC to Statistics RX Byte Valid
Indicator
TxClientClk_1
Statistics 1
O
0
TEMAC to Statistics TX Clock
ClientTxStat_1
Statistics 1
O
0
TEMAC to Statistics TX Data
ClientTxStatsVld_1
Statistics 1
O
0
TEMAC to Statistics TX Valid
Indicator
ClientTxStatsByteVld_1
Statistics 1
O
0
TEMAC to Statistics TX Byte Valid
Indicator
RxClientClk_1
Statistics 1
O
0
TEMAC to Statistics RX Clock
ClientRxStats_1(6:0)
Statistics 1
O
0
TEMAC to Statistics RX Data
ClientRxStatsVld_1
Statistics 1
O
0
TEMAC to Statistics RX Valid
Indicator
ClientRxStatsByteVld_1
Statistics 1
O
0
TEMAC to Statistics RX Byte Valid
Indicator
1. This core is designed with only synchronous resets. As a consequence of this design methodology, slower clock domains will come
out of reset before fast clock domains. For most systems this is not an issue, but for 10 Mbs operation, the slower tx client Ethernet
core clock can be as low as 1.25 MHz. With such a slow clock and PLB running at 125 MHz, the circuit on the 1.25 MHz clock will
come out of reset up to 800 ns (or 100 PLB clock periods) after the PLB clock domain comes out of reset. To insure proper core
behavior, the TEMAC core should not be accessed for at least 800 ns after PLB reset.
2. The LocalLink clock must be equal to or greater than half the frequency of the Ethernet data on the PHY interface. When using a
1000 Mbs Ethernet bus speed, the PHY data clock is 125 MHz so the LocalLink clock must be 62.5 MHz or greater (faster). When
using a 100 Mbs Ethernet bus speed, the PHY data clock is 25 MHz so the LocalLink clock must be 12.5 MHz or greater. When
using a 10 Mbs Ethernet bus speed, the PHY data clock is 2.5 MHz so the LocalLink clock must be 1.25 MHz or greater.
3. When Ethernet statistics are enabled with the Virtex-6, Virtex-5, Virtex-4, and Spartan-3 device families, the Ethernet statistics
core’s reference clock is connected to REFCLK.
4. When Ethernet statistics are enabled with the Spartan-6 device family, the Ethernet statistics core’s reference clock is connected
to GTX_CLK_0.
5. Please refer to the 1000BASE-X Auto-Negotiation section for information on example system.ucf constraints that may be used to
allow 125 MHz clocks in Virtex-4 and their limitations.
6. The Host Interface Signals are not used at this time and should always remain unconnected.
Clock Pin Selection
When targeting a GMII design, it uses a BUFGMUX to switch between the MII_TX_CLK and the GTX_CLK. This
allows for the design to support data rates of 10/100 Mbps and also 1000 Mbps The FPGA pins for these clocks must
be selected such that they are located in the same clock region and they are both on clock dedicated pins. The GMII
status, control, and data pins must be chosen to be in the same clock region as the above mentioned clocks. Please
refer to the appropriate FPGA Family Clocking Resources User Guide for more information. Please pay special
attention to clocking conflicts. Failure to adhere to these rules will result in build errors and data integrity errors.
Design Parameters
To allow the user to generate an XPS_LL_TEMAC that is uniquely tailored the user’s system, certain features can be
parameterized in the XPS_LL_TEMAC design as shown in Table 4.
Table 4: XPS_LL_TEMAC Design Parameters
Feature/Description
Parameter Name
Allowable Values
User Specified PLB Bus Implementation Parameters
Default Values
VHDL
Type
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