DS537 Datasheet, PDF (31/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 12: Interrupt Status Register Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
1. Please refer to Figure 50 on page 80 for conditions that will cause the receive frame reject interrupt to occur. The receive frame
reject interrupt will occur for any of the following reasons:
A. The frame does not meet the Ethernet frame requirements as determined by the hard TEMAC core (bad FCS, bad length, etc).
B. In addition to the frame being good but not meeting the destination address filtering by the hard TEMAC, the frame also does
not match one of the 4 multicast table entries, it is not a broadcast frame, it does not match the unicast address register, and the
Hard TEMAC core is not in promiscuous mode.
C. The core was built to support extended multicast address filtering (C_TEMACx_MCAST_EXTEND=1), but the hard TEMAC
core is not in promiscuous mode.
D. The frame is good and meets the destination address filtering by the hard TEMAC but it is a multicast frame and the multicast
reject bit is set in the soft RAF register.
E. The frame is good and meets the destination address filtering by the hard TEMAC but it is a broadcast frame and the broadcast
reject bit is set in the soft RAF register.
2. This bit will reset to ’0’ but may change to ’1’ immediately after reset is removed. This bit may remain at ’0’ for some time in systems
that are using MGTs when the MGTs are not yet ready for use.
X-Ref Target - Figure 9
Reserved ^{CfgWCenfgReAnfWeAnfMReiimn MWieimnRFeanbrRen}
...
...
TIS Register
25 26 27 28 29 30 31 ADDRESS_CODE
0x3A0 R/W
TIE Register
25 26 27 28 29 30 31 ADDRESS_CODE
0x3A4 R/W
OR
ReservMRegxdtDRcdmy0LoTcxkCR0mxpFlitf0oORvxrR0RjexcCt0mA^{uptlot0Neg0 HardAcsCmplt}
...
...
...
IS0 Register
24 25 26 27 28 29 30 31 ^offset
0x00C R/W
IE0 Register
24 25 26 27 28 29 30 31 offset
0x014 R/W
IP0 Register
24 25 26 27 28 29 30 31 offset
0x010 R
OR
Reserved ^{CfgWCenfgReAnfWeAnfMReiimn MWieimnRFeanbrRen}
...
...
TIS Register
25 26 27 28 29 30 31 ADDRESS_CODE
0x3A0 R/W
TIE Register
25 26 27 28 29 30 31 ADDRESS_CODE
0x3A4 R/W
OR
ReservMRegxdtDRcdmy1LoTcxkCR1mxpFlitf1oORvxrR1 ^{RjexcCt1mAuptlot1Neg1 HardAcsCmplt}
...
...
...
IS1 Register
24 25 26 27 28 29 30 31 ^offset
0x04C R/W
IE1 Register
24 25 26 27 28 29 30 31 offset
0x054 R/W
IP1 Register
24 25 26 27 28 29 30 31 offset
0x050 R
OR
TemacIntc_Irpt0
TemacIntc_Irpt1
Figure 9: XPS_LL_TEMAC Interrupt Structure
DS537_09_091909
Interrupt Pending Registers (IP0 and IP1)
The Interrupt Pending Register is shown in Figure 10. This register combined with the IS, IE, TIS, and TIE registers
define the interrupt interface of the XPS_LL_TEMAC. The Interrupt Pending register uses one bit to represent each
XPS_LL_TEMAC internal interruptible condition that is represented in the Interrupt Status Register.
If one or more interrupt is latched in the Interrupt Status Register and corresponding enable bits are set in the
Interrupt Enable Register, then the corresponding bit is set in the Interrupt Pending Register. If one or more bits is
set in the Interrupt Pending register then the TemacIntc_Irpt signal is driven active high out of the
XPS_LL_TEMAC. A separate IP register exists for TEMAC interface 0 and TEMAC interface 1.
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