DS537 Datasheet, PDF (13/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 3: I/O Signal Description
Signal Name
Interface
Signal
Type
Init
Status
Description
GMII_RX_DV_1
Ethernet bus
1 GMII
I
PHY to TEMAC receive data valid
indicator
GMII_RX_ER_1
Ethernet bus
1 GMII
I
PHY to TEMAC receive error
indicator
GMII_RX_CLK_1
Ethernet bus
1 GMII
I
PHY to TEMAC receive clock
Ethernet Channel 0 SGMII and 1000Base-X Signals
TXP_0
Ethernet bus
0 SGMII and
O
1000Base-X
TEMAC to PHY transmit data
0
positive
TXN_0
Ethernet bus
0 SGMII and
O
1000Base-X
TEMAC to PHY transmit data
0
negative
RXP_0
Ethernet bus
0 SGMII and
I
1000Base-X
PHY to TEMAC receive data positive
RXN_0
Ethernet bus
0 SGMII and
I
1000Base-X
PHY to TEMAC receive data
negative
Ethernet Channel 1 SGMII and 1000Base-X Signals
TXP_1
Ethernet bus
1 SGMII and
O
1000Base-X
TEMAC to PHY transmit data
0
positive
TXN_1
Ethernet bus
1 SGMII and
O
1000Base-X
TEMAC to PHY transmit data
0
negative
RXP_1
Ethernet bus
1 SGMII and
I
1000Base-X
PHY to TEMAC receive data positive
RXN_1
Ethernet bus
1 SGMII and
I
1000Base-X
PHY to TEMAC receive data
negative
Ethernet Channel 0 RGMII Signals
RGMII_TXD_0(3:0)
Ethernet bus
0 RGMII
O
0
TEMAC to PHY transmit data
RGMII_TX_CTL_0
Ethernet bus
0 RGMII
O
0
TEMAC to PHY transmit control
RGMII_TXC_0
Ethernet bus
0 RGMII
O
0
TEMAC to PHY transmit clock
RGMII_RXD_0(3:0)
Ethernet bus
0 RGMII
I
PHY to TEMAC receive data
RGMII_RX_CTL_0
Ethernet bus
0 RGMII
I
PHY to TEMAC receive control
RGMII_RXC_0
Ethernet bus
0 RGMII
I
PHY to TEMAC receive clock
Ethernet Channel 1 RGMII Signals
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