DS537 Datasheet, PDF (58/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 34 shows the TEMAC Management Configuration Registers bit definitions.
Table 34: TEMAC Management Configuration Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
7 - 31 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
MDIO Enable. When this bit is "1", the MDIO (MII Management) interface is
used to access the PHY.
6
MDIOEN Read/Write
0
0 - MDIO disabled
1 - MDIO enabled
0-5
CLOCK
DIVIDE
Read/Write
0x0
Clock Divide. This value is used to derive the MDC (MII Management
interface clock) signal. The maximum permitted frequency is 2.5 MHz.
TEMAC Unicast Address Word 0 (UAW0) Registers
The TEMAC Unicast Address Word 0 Register is shown in Figure 36. There is a separate register for each of the two
Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the address
used to access the LSW and CTL registers.
The Unicast Addresses Registers combine to provide a 48 bit Ethernet station address. Word 0 provides the low
order 32 bits of the address while word 1 provides the high order 16 bits.
This register’s reset value is slightly different for implementations using the soft TEMAC (C_TEMAC_TYPE = 2),
Virtex-4 hard TEMAC (C_TEMAC_TYPE = 1), Virtex-5 hard TEMAC (C_TEMAC_TYPE = 0), and Virtex-6 hard
TEMAC (C_TEMAC_TYPE = 3).
X-Ref Target - Figure 36
31
0
UnicastAddr(31:0)
DS537_36_091909
Figure 36: TEMAC Unicast Address Word 0 Registers (ADDRESS_CODE 0x380)
Table 35 shows the TEMAC Unicast Address Word 0 Registers bit definitions.
Table 35: TEMAC Unicast Address Word 0 Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset Value
Description
0 - 31 UnicastAddr Read/Write
0xDDCCBBAA
0xFFFFFFFF⁽¹⁾
Unicast Address (31:0). This address is used to match against
the destination address of any received frames.
The address is ordered so the first byte transmitted/received is the
lowest positioned byte in the register; for example, a MAC address
of AA-BB-CC-DD-EE-FF would be stored in UnicastAddr(47:0) as
0xFFEEDDCCBBAA.
1. This register will return a different reset value for different TEMAC implementations. The soft TEMAC implementation will return a
0xFFFFFFFF while the Virtex-4 hard TEMAC, Virtex-5 hard TEMAC and Virtex-6 hard TEMAC implementations will return a
0xDDCCBBAA.
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