DS537 Datasheet, PDF (82/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Additional registers Unicast Address Word Lower Register (UAWL0 and UAWL1) and Unicast Address Word Upper
Register (UAWU0 and UAWU1) are available to provide unicast address filtering while in this mode.
For builds that have the extended multicast address filtering enabled, promiscuous mode can be achieved by
making sure that the TEMAC is in promiscuous mode and by clearing the EMultiFltrEnbl bit (bit 19) in the Reset
and Address Filter Registers (RAF0 and RAF1).
When a received frame is accepted and passed up to software, additional information is provided in the receive
LocalLink footer words to help the software perform the additional address filtering with less overhead.
Receive LocalLink footer words 3 and 4 include the destination address of the frame and footer word 5 includes bits
to indicate if the frame had a destination address that was the broadcast address, a MAC multicast address, or an IP
multicast address (and if none of those bits are set, it was a unicast address). Please see the section on Receive
LocalLink Frame Format for more information.
This allows the software to make decisions about the destination address without accessing the address from within
the payload of the LocalLink transfer among the other frame data. When using a Xilinx DMA core, this means the
information needed by the software for filtering is in the buffer descriptor and a decision can be made regarding
accepting or rejecting the frame without accessing the data buffer itself thus reducing memory access and buffer
indexing overhead.
Flow Control
The flow control function is defined by IEEE Std 802.3-2002 Clause 31. The XPS_LL_TEMAC can be configured to
send pause frames and to act upon the pause frames received. These two behaviors can be configured
independently (asymmetrically). To enable or disable transmit and receive flow control, refer to the FCC register
(page 54).
Flow control can be used to prevent data loss when an Ethernet interface is unable to process frames fast enough to
keep up with the rate of frames provided by another Ethernet interface. When this occurs, the Ethernet interface
that requires relief can transmit a pause control frame to the link partner to request it cease transmitting for a
defined period of time.
Transmitting a Pause Control Frame
For the XPS_LL_TEMAC, a pause frame transmission can be initiated by writing a pause value to the TPF register
(page 28) while transmit pause processing is enabled (FCC register bit 30 is 1 page 54).
Requesting the transmit of a pause frame will not interrupt a transmission in progress but the pause frame will be
transmitted after the frame in progress. A request to transmit a pause frame will result in the transmission of a
pause frame even if the transmitter itself is already paused due to the reception of a pause frame.
The destination address supplied with the transmitted pause control frame can be set by writing to the RCW0 and
RCW1 registers (page 50).
Receiving a Pause Control Frame
When an error free frame is received by the XPS_LL_TEMAC, it examines the following information:
1. The destination address field is compared to the pause control address and the configured unicast address.
2. The Length/Type field is compared against the control type code (0x8808).
3. The opcode field contents are matched against the pause control opcode (0x0001).
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