DS537 Datasheet, PDF (56/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 32: TEMAC Ethernet MAC Mode Configuration Registers Bit Definitions (Cont’d)
Bit(s)
Name
Core Access
Reset
Value
Description
0 - 20 Reserved ^Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
1. The entire contents of this register are Read/Write accessible for the Virtex-6 hard TEMAC configuration, but only bits 31-30 are
Read/Write accessible in Virtex-4, Virtex-5, and Soft TEMAC configurations
2. The Reset Value for LINK SPEED is “10” or 1000 Mb/s for all PHY interfaces except for MII which is not capable of that speed. The
Reset Value for LINK SPEED for the MII interface is “01” or 100 Mb/s.
3. The use or not of the Host interface is hidden from the user and is of no concern. However, this register will return a different reset
value for different TEMAC implementations. The soft TEMAC implementation will return a ’0’ while the Virtex-4 hard TEMAC,
Virtex-5 hard TEMAC, and Virtex-6 hard TEMAC implementations will return a ’1’.
TEMAC RGMII/SGMII Configuration (PHYC) Registers
The TEMAC RGMII/SGMII Configuration Register is shown in Figure 34. There is a separate register for each of the
two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the
address used to access the LSW and CTL registers.
X-Ref Target - Figure 34
RGMII HD
31 30
3 21 0
SGMII
Link Speed
Reserved
RGMII
RGMII Link
Link Speed
DS537_34_091909
Figure 34: TEMAC RGMII/SGMII Configuration Registers (ADDRESS_CODE 0x320)
Table 33 shows the TEMAC RGMII/SGMII Configuration Registers bit definitions.
Table 33: TEMAC RGMII/SGMII Configuration Registers Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
31 - 30
SGMII Link
Speed
Read
SGMII Link Speed. Valid in SGMII mode only. This displays the SGMII speed
information as received from auto negotiation by the speed field of the
PCS/PMA register 5 (Table 105).The speed of the Ethernet interface is
defined by the following values.
0x0 _{10 - 1000 Mb/S}
01 - 100 Mb/S
00 - 10 Mb/s
11 - N/A
4 - 29 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always return
zero.
2-3
RGMII Link
Speed
Read
RGMII Link Speed. Valid in RGMII mode only. This displays the RGMII speed
information as encoded by the PHY to the TEMAC by GMII_RX_DV and
GMII_RX_ER during the IFG. The speed of the Ethernet interface is defined
by the following values.
0x0 _{10 - 1000 Mb/S}
01 - 100 Mb/S
00 - 10 Mb/s
11 - N/A
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