DS537 Datasheet, PDF (12/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 3: I/O Signal Description
Signal Name
MII_TXD_1(3:0)
MII_TX_EN_1
MII_TX_ER_1
MII_RXD_1(3:0)
MII_RX_DV_1
MII_RX_ER_1
MII_RX_CLK_1
MII_TX_CLK_1
GMII_TXD_0(7:0)
GMII_TX_EN_0
GMII_TX_ER_0
GMII_TX_CLK_0
GMII_RXD_0(7:0)
GMII_RX_DV_0
GMII_RX_ER_0
GMII_RX_CLK_0
GMII_TXD_1(7:0)
GMII_TX_EN_1
GMII_TX_ER_1
GMII_TX_CLK_1
GMII_RXD_1(7:0)
Interface
Signal
Type
Init
Status
Ethernet Channel 1 MII Signals
Ethernet bus
1 MII
O
0
Ethernet bus
1MII
O
0
Ethernet bus
1 MII
O
0
Ethernet bus
1 MII
I
Ethernet bus
1 MII
I
Ethernet bus
1 MII
I
Ethernet bus
1 MII
I
Ethernet bus
1 MII
I
Ethernet Channel 0 GMII Signals
Ethernet bus
0 GMII
O
0
Ethernet bus
0 GMII
O
0
Ethernet bus
0 GMII
O
0
Ethernet bus
0 GMII
O
0
Ethernet bus
0 GMII
I
Ethernet bus
0 GMII
I
Ethernet bus
0 GMII
I
Ethernet bus
0 GMII
I
Ethernet Channel 1 GMII Signals
Ethernet bus
1 GMII
O
0
Ethernet bus
1 GMII
O
0
Ethernet bus
1 GMII
O
0
Ethernet bus
1 GMII
O
0
Ethernet bus
1 GMII
I
Description
TEMAC to PHY transmit data
TEMAC to PHY transmit enable
TEMAC to PHY transmit Error
enable
PHY to TEMAC receive data
PHY to TEMAC receive data valid
indicator
PHY to TEMAC receive error
indicator
PHY to TEMAC receive clock
PHY to TEMAC transmit clock (also
used for GMII/MII mode)
TEMAC to PHY transmit data
TEMAC to PHY transmit enable
TEMAC to PHY transmit Error
enable
TEMAC to PHY transmit clock
PHY to TEMAC receive data
PHY to TEMAC receive data valid
indicator
PHY to TEMAC receive error
indicator
PHY to TEMAC receive clock
TEMAC to PHY transmit data
TEMAC to PHY transmit enable
TEMAC to PHY transmit Error
enable
TEMAC to PHY transmit clock
PHY to TEMAC receive data
www.xilinx.com
12