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DS537 Datasheet, PDF (147/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC
LogiCORE IP XPS LL TEMAC (v2.03a)
Revision History
Date
8/31/07
9/28/07
10/1/07
10/3/07
10/12/07
1/22/08
2/07/08
4/16/08
4/22/08
7/03/08
2/17/09
3/03/09
3/31/09
6/24/09
7/17/09
12/2/09
12/10/09
4/01/10
5/17/10
6/23/10
12/14/10
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.7
1.8
1.9
1.10
1.11
1.12
2.0
2.1
2.2
2.3
2.4
2.5
2.6
Revision
Initial Xilinx release.
Update for new revision and to add MII to soft TEMAC implementation as well as UCF constraint
information and update clocking circuitry diagrams.
Added FMAX Margin System Performance section.
Updated clocking circuitry diagrams, constraint information and implementation resource
information.
Updated to core revision to 1.01a.
Final updates for release.
Updated core revision to 1.01b.
Added Automotive Spartan-3E, Automotive Spartan-3A, and Automotive Spartan-3A DSP
support.
Final updates for release.
Updated RGMII clock diagrams and RGMII and GMII constraints to match design.
Updated with new functions for core version 2.00a.
Updated with new functions for core version 2.01a.
Updated for revision change to 2.01b.
Updated to v2.02a for EDK_L 11.2 release: updated legal matter and copyright information, moved
constraint examples to AR#32713, removed C_INCLUDE_IO diagrams and reference User
Guides, updated supported devices.
Added Ethernet AVB to features, updated resource usage, added Hard TEMAC dependency with
C_INCLUDE_IO parameter, updated Margin System figures.
Updated core revision to 2.03a for EDK_L 11.4 release; updated images; converted to current data
sheet template. Incorporated CR523738 by adding clarification that half-duplex is not supported.
Incorporated CR523738 to add clarification that half-duplex is not supported.
Update V6 and S6 resource utilization tables Table 138 and Table 141 to indicate 6-Input LUTs.
Incorporated CR560051 (C_INCLUDE_IO with Soft TEMAC)
Incorporated CR480350 to update SOP and EOP terminology.
Incorporated CR573050 to add Clock Pin Selection section.
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