DS537 Datasheet, PDF (47/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
TEMAC Control (shared) Register (CTL)
The Control Register is shown in Figure 26. Writing to this register initiates a write to or read from the indirectly
addressable registers. If it is a write operation, the LSW must be provided with the write value prior to writing to
this register. This register is shared between the Ethernet Interface 0 and Ethernet Interface 1 even though each
interface has its own address for this register.
It is important to note that once an access has been initiated to an indirectly addressed location, the interface will
ignore any additional requests for indirect register accesses until the current access is complete. Therefore, it is
essential to determine that the current access is complete before issuing a new indirect access command. While
some indirect accesses will complete in one clock cycle, others such as accessing PHY registers from the MII
Management interface will require many clock cycles.
Determining that an indirect access is complete can be accomplished with two methods using either polling or
interrupts.
1. An interrupt indicates that the access is complete. The interrupt HardAcsCmplt must be enabled in the TIE
register as well as the IE register. The interrupt must be cleared as described later in this document in the section
discussing the interrupt registers.
2. Polling the ready status register (RDY) to determine if the access is complete. The bits in this register are
asserted when there is no access in progress. When an access is in progress, a bit corresponding to the type of
access is de-asserted. When the access is complete, the bit is re-asserted.
X-Ref Target - Figure 26
WEN
ADDRESS_CODE
16
22
31
Reserved
Reserved
DS537_26_091909
Figure 26: TEMAC Control Register (offset 0x028 or 0x068)
Table 25 shows the TEMAC Control Register bit definitions.
Table 25: TEMAC Control Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
22 - 31 ADDRESS_CODE Read/Write 0x0
17 - 21
Reserved
Read
0x0
16
WEN
Read/Write
0
0 - 15
Reserved
Read
0x0
Description
Address Code. The address in this field selects the indirectly
addressable register that will be access with a read or a write as
shown in Table 8, page 23 and Figure 4, page 24.
Reserved. These bits are reserved for future definition and will always
return zero.
Write Enable. When this bit is asserted, the data in the LSW register
is written to the register indicated by the ADDRESS_CODE field.
0 - read operation
1 - write operation
Reserved. These bits are reserved for future definition and will always
return zero.
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