DS537 Datasheet, PDF (23/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
The directly addressable TEMAC registers in Table 7 are used to indirectly access all of the other TEMAC registers
(Table 8) and the internal and external PHY registers (via the MII management bus interface).
The indirectly addresses registers for TEMAC interface 0 and interface 1 share the same ADDRESS_CODE field
value. The use of CTL0 register or CTL1 register determines which TEMAC interface register is accessed. For
example, a ADDRESS_CODE field value of 0x200 is used to access the Receive Configuration Word 0 register. If this
address is placed in the CTL0 register then the TEMAC interface 0 register will be accessed. If the address is placed
in the CTL1 register then the TEMAC interface 1 register will be accessed.
It is important to note that once an access has been initiated to an indirectly addressed location, the interface will
ignore any additional requests for indirect register accesses until the current access is complete. Therefore, it is
essential to determine that the current access is complete before issuing a new indirect access command. While
some indirect accesses will complete in one clock cycle, others such as accessing PHY registers from the MII
Management interface will require many clock cycles.
Determining that an indirect access is complete can be accomplished with two methods using either polling or
interrupts.
1. An interrupt indicates that the access is complete. The interrupt HardAcsCmplt must be enabled in the TIE
register as well as the IE register. The interrupt must be cleared as described later in this document in the section
discussing the interrupt registers.
2. Polling the ready status register (RDY) to determine if the access is complete. The bits in this register are
asserted when there is no access in progress. When an access is in progress, a bit corresponding to the type of
access is de-asserted. When the access is complete, the bit is re-asserted.
Table 8: XPS_LL_TEMAC PLB Indirectly Addressable TEMAC Registers
Register Name
ADDRESS_CODE field of CTL0 or
CTL1 register (10 bits)
Unused
0x000 - 0x02F
Unused
0x040 - 0x04F
TEMAC0 or TEMAC1 Receive Configuration Word 0
Register (RCW0)
0x200
TEMAC0 or TEMAC1 Receive Configuration Word 1
Register (RCW1)
0x240
TEMAC0 or TEMAC1 Transmitter Configuration
Register (TC)
0x280
TEMAC0 or TEMAC1 Flow Control Configuration
Register (FCC)
0x2C0
TEMAC0 or TEMAC1 Ethernet MAC Mode
Configuration Register (EMMC)
0x300
TEMAC0 or TEMAC1 RGMII/SGMII Configuration
Register (PHYC)
0x320
TEMAC0 or TEMAC1 Management Configuration
Register (MC)
0x340
TEMAC0 or TEMAC1 Unicast Address Word 0
Register (UAW0)
0x380
TEMAC0 or TEMAC1 Unicast Address Word 1
Register (UAW1)
0x384
TEMAC0 or TEMAC1 Multicast Address Table
Access Word 0 Register (MAW0)
0x388
Access
Read
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read except bits 30 and
31 which are Read/Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
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