DS537 Datasheet, PDF (108/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
The RGMII design uses clock enables. Please refer to UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC
User Guide for an equivalent diagram of the clock management scheme when the XPS_LL_TEMAC parameter
C_INCLUDE_IO = “1” for both RGMII Version 2.0 and RGMII Version 1.3. When the parameter C_INCLUDE_IO =
“0”, the BUFG and IDELAY on the RGMII_RXC signal are not used.
Virtex 5 Hard TEMAC RGMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Serial Gigabit Media Independent Interface (SGMII)
The Serial-GMII (SGMII) is an alternative interface to the GMII/MII that converts the parallel interface of the GMII
into a serial format. This radically reduces the I/O count and is therefore often favored by PCB designers. This is
achieved by using a RocketIO transceiver.
SGMII can carry Ethernet traffic at 10 Mb/S, 100 Mb/S, and 1 Gb/S.
The SGMII physical interface was defined by Cisco Systems. The data signals operate at a rate of 1.25 Gb/S.
Differential pairs are used to provide signal integrity and minimize noise. The sideband clock signals defined in the
specification are not implemented in the XPS_LL_TEMAC. Instead, the RocketIO MGT is used to transmit and
receive the differential data at the required rate using clock data recovery. For more information on SGMII, refer to
the Serial GMII Specification v1.7.
Please refer to UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide for an equivalent diagram of
the clock management scheme when the XPS_LL_TEMAC parameter C_INCLUDE_IO = “1”. When the parameter
C_INCLUDE_IO = “0”, When the parameter C_INCLUDE_IO = “0”, MGTCLK_P connects directly to the RocketIO
GTP/GTX; hence the IBUFDS is not used.
Virtex 5 Hard TEMAC SGMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
SGMII Auto-Negotiation
The external SGMII capable PHY device performs auto negotiation with its link partner on the PHY Link (Ethernet
bus) resolving operational speed and duplex mode and then in turn performs a secondary auto negotiation with the
RocketIO transceiver across the SGMII Link. This transfers the results of the PHY with Link Partner auto
negotiation across the SGMII to the XPS_LL_TEMAC.
The results of the SGMII auto negotiation can be read from the SGMII Management Auto negotiation Link Partner
Ability Base Register (Table 105). The duplex mode and speed of the XPS_LL_TEMAC should then be set to match
(see TEMAC Receive Configuration Word 1 (RCW1) Registers, page 51, TEMAC Transmit Configuration (TC)
Registers, page 52, and TEMAC Ethernet MAC Mode Configuration (EMMC) Registers, page 54).
There are two methods that may be used to learn of the completion of an auto negotiation cycle:
By polling the auto negotiation complete bit of SGMII Management Status Register (Register 1, bit 5 Table 101).
By using the auto negotiation complete interrupt (Interrupt Status Registers (IS0 and IS1), page 29 and SGMII
Management Auto Negotiation Interrupt Control Register Table 110 on page 121.)
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