DS537 Datasheet, PDF (39/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
up to software for a comparison on the full 23-bit address. If the memory location is a 0 or the upper 24 bits are not
01:00:5E then the frame is not accepted and it is dropped.
The memory is 1-bit wide but is addressed on 32-bit word boundaries. The memory is 32K deep. This table must be
initialized by software via the PLB interface
When using the extended multicast address filtering, the TEMAC must be set to promiscuous mode so that all
frames are available for filtering. When doing this the TEMAC no longer checks for a unicast address match.
Additional registers (UAWLx and UAWUx) are available to provide unicast address filtering while in this mode.
For builds that have the extended multicast address filtering enabled, promiscuous mode can be achieved by
making sure that the TEMAC is in promiscuous mode and by clearing the EMultiFltrEnbl bit (bit 19) in the Reset
and Address Filter register (RAF).
Please see the section on Extended Multicast Filtering for more details (Extended Multicast Address Filtering Mode,
page 80).
X-Ref Target - Figure 19
Reserved
McastAdrEnbl
31
DS537_19_091909
Figure 19: Multicast Address Table entry (offset 0x20000-0x3FFFF and 0x60000-0x7FFFF)
Table 21 shows the Multicast Address Table bit definitions.
Table 21: Multicast Address Table Bit Definitions
Bit(s)
Name
Core
Reset
Access Value
Description
31 McastAdrEnbl Read/Write
Multicast Address Enable. This bit indicates that the received multicast
frame with this upper 15 bits of the unique 23-bit MAC multicast address
0 ^{field should be accepted or rejected.}
0 - Drop this frame
1 - Accept this frame
0 - 30 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
Transmit VLAN Data Table (0 and 1)
This table is used for data to support transmit VLAN tagging, VLAN stripping, and VLAN translation. The table is
always 4K entries deep but the width depends on how many of the VLAN functions are included at build time.
VLAN translation requires 12 bits at each location while VLAN stripping and VLAN tagging require 1 bit each at
each location.
When all transmit VLAN functions are included, the table is 14 bits wide. If VLAN functions are not included, the
bits for those functions will not be present and writes to those bits will have no effect while reads will return zero.
The table may be either 1-bit, 2-bits, 12-bits, 13-bits, or 14-bits wide depending on which features are present. The
table must be initialized by software via the PLB and is addressed on 32-bit word boundaries.
The transmit VLAN Table entry with all VLAN functions present is shown in Figure 20 while Figure 21 shows the
transmit VLAN Table entry with only the translation field. Note that the bit locations for the functions do not
change even when some functions are not used in the build.
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