DS537 Datasheet, PDF (106/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 83 shows the Hard TEMAC Internal SGMII PCS Management Extended Status Register bit definitions.
Table 83: SGMII Management Extended Status Register (Register 15) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
15
1000BASE-X
Full Duplex
Returns 1
1
Always returns a 1 for this bit because 1000BASE-X full duplex is
supported.
14
1000BASE-X
Half Duplex
Returns 0
0
Always returns a 1 for this bit because 1000BASE-X half duplex is not
supported.
13
1000BASE-T
Full Duplex
Returns 0
0
Always returns a 1 for this bit because 1000BASE-T full duplex is not
supported.
12
1000BASE-T
Half Duplex
Returns 0
0
Always returns a 1 for this bit because 1000BASE-T half duplex is not
supported.
0 - 11 Reserved Returns 0s 0x0 Always return zeros.
Table 84 shows the Hard TEMAC Internal SGMII PCS Management Auto Negotiation Interrupt Control Register bit
definitions.
Table 84: SGMII Management Auto Negotiation Interrupt Control Register (Register 16) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
2 - 15 Reserved Returns 0s
0 Always return zeros.
If the interrupt is enabled, this bit will be asserted upon the completion of an
auto negotiation cycle; it will only be cleared by writing 0 to this bit. If the
1
Interrupt
Status
Read/Write
interrupt is disabled, this bit will be set to 0. This is the auto negotiation
0
complete interrupt.
0 - interrupt is asserted
1 - interrupt is not asserted
0
Interrupt
Enable
Read/Write
1
0 - interrupt is disabled
1 - interrupt is enabled
Table 85 shows the Hard TEMAC Internal SGMII PCS Management Loopback Control Register bit definitions.
Table 85: SGMII Management Loopback Control Register (Register 17) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
1 - 15 Reserved Returns 0s
0 Always return zeros.
Loopback is enabled or disabled using register 0 bit 14.
0
Loopback
Position
Read/Write
0
0 - loopback (when enabled) occurs directly before the interface to the
RocketIO transceiver
1 - loopback (when enabled) occurs in the RocketIO transceiver
Virtex-5 Hard TEMAC Implementations
Introduction to Physical Interfaces
The Hard TEMAC silicon component in the Virtex-5 FPGA devices is independent of, and can connect to, any type
of physical layer device. The XPS_LL_TEMAC provides additional circuitry around the Hard TEMAC silicon
component to allow easy use of several common physical layer device interfaces.
www.xilinx.com
106