DS537 Datasheet, PDF (101/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 71 shows the Hard TEMAC Internal 1000BASE-X PCS/PMA Management Auto Negotiation Interrupt
Control Register bit definitions.
Table 71: 1000BASE-X Management Auto Negotiation Interrupt Control Register (Register 16) Bit
Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
2 - 15 Reserved Returns 0s
0 Always return zeros.
If the interrupt is enabled, this bit will be asserted upon the completion of an
auto negotiation cycle; it will only be cleared by writing 0 to this bit. If the
1
Interrupt
Status
Read/Write
interrupt is disabled, this bit will be set to 0. This is the auto negotiation
0
complete interrupt.
0 - interrupt is asserted
1 - interrupt is not asserted
0
Interrupt
Enable
Read/Write
0 - interrupt is disabled
1
1 - interrupt is enabled
Table 72 shows the Hard TEMAC Internal 1000BASE-X PCS/PMA Management Loopback Control Register bit
definitions.
Table 72: 1000BASE-X Management Loopback Control Register (Register 17) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
1 - 15 Reserved Returns 0s
0 Always return zeros.
Loopback is enabled or disabled using register 0 bit 14.
0
Loopback
Position
Read/Write
0
0 - loopback (when enabled) occurs directly before the interface to the
RocketIO transceiver
1 - loopback (when enabled) occurs in the RocketIO transceiver
Internal SGMII Management Registers
Registers 0 through 15 are defined in IEEE 802.3. These registers contain information relating to the operation of the
SGMII PCS sublayer, including the status of both the SGMII Link and the physical Ethernet link (PHY Link).
Additionally, these registers are directly involved in the operation of the SGMII auto negotiation function which
occurs between the XPS_LL_TEMAC and the external PHY device (typically a tri-speed BASE-T PHY).
These registers are accessed via the MII Management interface (Using the MII Management to Access Internal or
External PHY Registers, page 67). These registers are only valid when using the SGMII PHY interface.
www.xilinx.com
101