DS537 Datasheet, PDF (91/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Order of VLAN Functions when Combined
When multiple VLAN functions are combined, the order of processing for both transmit and receive shall be:
1. VLAN Stripping
2. VLAN Translation
3. VLAN Tagging
X-Ref Target - Figure 59
RX
Additional
Validation
and
Addr Filtering
VLAN
Stripping
VLAN
VLAN
Translation Tagging
Local-
Link
Local-
Link
VLAN
Stripping
VLAN
VLAN
Translation Tagging
TX
DS537_59_091909
Figure 59: Order of Extended VLAN Functions
Ethernet Audio Video Bridging (AVB)
Ethernet AVB functionality is supported with XPS_LL_TEMAC; however, the LogicCORE IP Ethernet AVB
Endpoint must be generated as a pcore and manually connected to the XPS_LL_TEMAC with the AVB functionality
enabled.
Please refer to UG492 LogicCORE IP Ethernet AVB Endpoint for more information on AVB.
Virtex-6 Hard TEMAC Implementations
Introduction to Physical Interfaces
The Hard TEMAC silicon component in the Virtex-6 FPGA devices is independent of, and can connect to, any type
of physical layer device. The XPS_LL_TEMAC provides additional circuitry around the Hard TEMAC silicon
component to allow easy use of several common physical layer device interfaces.
The following are two types of physical layer interfaces:
• BASE-T provide a link between the XPS_LL_TEMAC and copper mediums. This functionality can be provided
in a XPS_LL_TEMAC system by connecting to external BASE_T PHY devices which are readily available. This
connection can be made using MII, GMII/MII, RGMII, and SGMII interfaces.
- Virtex-6 devices support GMII/MII at 2.5 V only.
• BASE-X provide a link between the XPS_LL_TEMAC and (usually) fiber optic mediums. The XPS_LL_TEMAC
system can provide this function at 1000 Mb/S (1000BASE-X) by using a RocketIO transceiver.
More information will be added as it becomes available.
Media Independent Interface (MII)
The Media Independent Interface (MII), defined in IEEE 802.3 clause 22, is a parallel interface that connects at
10-Mb/S and/or 100-Mb/S to external PHY devices.
The MII design uses clock enables. Please refer to UG368 Virtex-6 Embedded Tri-Mode Ethernet MAC User Guide
for an equivalent diagram of the clock management scheme when the XPS_LL_TEMAC parameter
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