DS537 Datasheet, PDF (68/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
To access the internal SGMII or 1000BASE-X registers, the PHYAD should match that set by parameters
C_TEMAC0_PHYADDR or C_TEMAC1_PHYADDR.
X-Ref Target - Figure 45
LSW register
Reserved
22
26 27
31
PHYAD(4:0) REGAD(4:0)
MII Management Write Data Register
Reserved
16
31
PHY (MII Management Interface slave device)
PHYAD 1
15 ^{PCS Sublayer Managed Register Block} 0
0
Control Register
1
Status Register
2
PHY Identifier Register
3
Phy Identifier Register
4_...
Auto negotiation Advertisement Register
PHY (MII Management Interface slave device)
PHYAD 2
15
0
1
2
3
4_...
PCS Sublayer Managed Register Block ₀
Control Register
Status Register
PHY Identifier Register
Phy Identifier Register
Auto negotiation Advertisement Register
DS537_45_091909
Figure 45: MII Management Write Register Field Mapping
Table 47 provides an example of a PHY register Write via the MII Management Interface.
Table 47: Example of a PHY Register Write via the MII Management Interface
Register Access
Value
Activity
LSW0
Write
0x0000ABCD
Write the value that will be written to the PHY register (we chose 0xABCD for this
case).
CTL0
Write
0x000083B0
Initiate the write to the MII Management Data register by setting the write enable
and providing the address for that indirectly addressed register.
LSW0
Write
0x00000062
Write the PHYAD (3 in this case) and REGAD (2 in this case) to the LSW register
for Ethernet interface 0.
CTL0
Write
0x000083B4
Initiate the write to the MII Management Access Initiate register by setting the
write enable and providing the address for that indirectly addressed register. This
will start the transaction on the MII Management Interface to the PHY.
RDY0
Read
0x0001007F
or
0x0000007B
Poll ready register for Ethernet interface 0 until we see 0x0001007F indicating
that the MII Management Interface write access is complete.
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