DS537 Datasheet, PDF (35/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
frame, this is the value that is added to the frame right after the source address field. Please see the section on VLAN
functions ("Extended VLAN Support" on page 85) for more information about how VLAN tagging is performed.
X-Ref Target - Figure 12
TPID
Priority CFI
VID
0
15 16 18 19 20
31
DS537_12_091909
Figure 12: Transmit VLAN Tag Register (offset 0x018 and 0x058)
Table 15 shows the Transmit VLAN Tag Register bit definitions.
Table 15: Transmit VLAN Tag register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
20 - 31 VID
Read/Write
0x0 VLAN identifier. Uniquely identifies the VLAN to which the frame belongs
19
CFI
Read/Write
0
Canonical Format Indicator.
16 - 18 Priority
Read/Write
0x0 User Priority.
0 - 15 TPID
Read/Write
0x0 Tag Protocol Identifier.
Receive VLAN Tag Register (RTAG0 and RTAG1)
The Receive VLAN Tag Register is shown in Figure 13. This register is only used when the VLAN tagging is
included in the core at build-time (C_TEMACx_RXVLAN_TAG = 1). When a VLAN tag is added to a receive frame,
this is the value that is added to the frame right after the source address field. Please see the section on VLAN
functions (Extended VLAN Support, page 85) for more information about how VLAN tagging is performed.
X-Ref Target - Figure 13
TPID
Priority CFI
VID
0
15 16 18 19 20
31
DS537_13_091909
Figure 13: Receive VLAN Tag Register (offset 0x01C and 0x05C)
Table 16 shows the Receive VLAN Tag Register bit definitions.
Table 16: Receive VLAN Tag register Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
20 - 31 VID
Read/Write
0x0 VLAN identifier. Uniquely identifies the VLAN to which the frame belongs
19
CFI
Read/Write
0
Canonical Format Indicator.
16 - 18 Priority
Read/Write
0x0 User Priority.
0 - 15 TPID
Read/Write
0x0 Tag Protocol Identifier.
Unicast Address Word Lower Register (UAWL0 and UAWL1)
The Unicast Address Word Lower Register is shown in Figure 14. This register and the following register are only
used when extended multicast filtering is included in the core at build-time (C_TEMACx_MCAST_EXTEND = 1)
and is enabled. These registers should not be confused with the UAW0 and UAW1 registers which are indirect
access registers inside the TEMAC core which are only used when extended multicast filtering is excluded in the
core at build-time or is disabled. When using extended multicast filtering, the TEMAC core must be placed in
www.xilinx.com
35