DS537 Datasheet, PDF (52/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 29: TEMAC Receive Configuration Word1 (RCW1) Registers Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
Receive Enable. When this bit is "1", the receiver logic is enabled to
operate. When this bit is "0", the receiver ignores activity on the receive
28
RX
Read/Write
1
interface.
0 - receive disabled
1 - receive enabled
VLAN Frame Enable. When this bit is "1", the receiver accepts VLAN
27
VLAN⁽²⁾
Read/Write
tagged frames. The maximum payload length increases by four bytes.
1
0 - receive of VLAN frames disabled
1 - receive of VLAN frames enabled
Half-Duplex Mode. When this bit is "1", the receive operates in half-duplex
mode. When this bit is "0", the receiver operates in full-duplex mode. Only
26
HD
Read/Write
0
full-duplex is supported so this bit should always be set to "0".
0 - full-duplex receive
1 - half-duplex receive (not supported)
Length/Type Field Valid Check Disable. When this bit is "1", it disables
the Length/Type field check on the receive frame.
25
LT_DIS
Read/Write
0
0 - perform Length/Type field check
1 - do not perform Length/Type field check
24 - 16 Reserved
Read
0x0
Reserved. These bits are reserved for future definition and will always
return zero.
15 - 0
PauseAddr
Read/Write
0xFFEE
Pause Frame Ethernet MAC Address (47:32). This address is used to
match the destination address of any received flow control frames. It is also
used as the source address for any transmitted flow control frames.
This address is ordered so that the first byte transmitted/ received is the
lowest position byte in the register. For example, a MAC address of
AA-BB-CC-DD-EE-FF would be stored in the PauseAddr(47:0) as
0xFFEEDDCCBBAA.
1. Extended VLAN function require that jumbo frames be enabled (1).
2. This bit enables basic VLAN operation that is native to the TEMAC core. The TEMAC core recognizes VLAN frames when the
Type/Length field contains a VLAN TAG with a TPID value of 0x8100. No other TPID values are recognized. Extended VLAN mode
described later allow programmable TPID values. This bit must be ’0’ (disabled) when using extended VLAN mode.
TEMAC Transmit Configuration (TC) Registers
The TEMAC Transmit Configuration Register is shown in Figure 31. There is a separate register for each of the two
Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the address
used to access the LSW and CTL registers. These registers can be written at any time but the transmitter logic will
only apply the configuration changes during Inter Frame gaps. The exception to this is the Reset bit which is
effective immediately.
X-Ref Target - Figure 31
JUM TX HD
31 30 29 28 27 26 25
RST FCS VLAN IFG
Reserved
DS537_31_091909
Figure 31: TEMAC Transmit Configuration Registers (ADDRESS_CODE 0x280)
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