DS537 Datasheet, PDF (57/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Table 33: TEMAC RGMII/SGMII Configuration Registers Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
1
RGMII HD
Read
RGMII Half-Duplex Mode. Valid in RGMII mode only. When this bit is "1", the
interface operates in half-duplex mode. When this bit is "0", the interface
operates in full-duplex mode. This information is encoded by the PHY to the
0
TEMAC by GMII_RX_DV and GMII_RX_ER during the IFG.
0 - full-duplex
1 - half-duplex
0
RGMII Link
Read
RGMII Link. Valid in RGMII mode only. When this bit is "1", the is up. When
this bit is "0", the link is down. This information is encoded by the PHY to the
0
TEMAC by GMII_RX_DV and GMII_RX_ER during the IFG.
0 - link is down
1 - link is up
TEMAC Management Configuration (MC) Registers
The TEMAC Management Configuration Register is shown in Figure 35. There is a separate register for each of the
two Ethernet Interfaces. Determination of which Ethernet Interface’s register is accessed is controlled by the
address used to access the LSW and CTL registers.
This register provides control for the TEMAC PHY MII management (MDIO) interface. The MDIO interface
supplies a clock to the external devices, MDC_0 and MDC_1. This clock is derived from the HostClk input signal
using the value in the Clock Divide[5:0].
The frequency of the MDIO clock is given by the following equation:
f_MDC = ₍---1----+------C----l--o---c--^f-k^H----^O_D----^S-i--^T_v---^C_i--d-^L--^K-e--[--5---:--0---]--₎----_×-----2-
To comply with the IEEE 802.3-2002 specification for this interface, the frequency of MDC_0 and MDC_1 should not
exceed 2.5 MHz.
To prevent MDC_0 and MDC_1 from being out of specification, the Clock Divide[5:0] value powers up at 000000.
While this value is in the register, it is impossible to enable the MDIO interface.
Even if the MDIO interface is enabled by setting bit 25 of this register, the MDIO port will still be disabled until a
non-zero value has been written into the clock divide field.
X-Ref Target - Figure 35
CLOCKDIVIDE
65
0
Reserved
MDIOEN
DS537_35_091909
Figure 35: TEMAC Management Configuration Registers (ADDRESS_CODE 0x340)
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