DS537 Datasheet, PDF (25/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Directly Addressable Memory and Soft Registers
Reset and Address Filter Registers (RAF0 and RAF1)
The Reset and Address Filter (RAF) Register is shown in Figure 5. This register allows the software to apply a reset
to the hard or soft TEMAC component and to block receive multicast and broadcast Ethernet frames. Additional
receive address filtering is provided with the indirectly addressable registers in Table 8. A separate RAF register
exists for TEMAC interface 0 and TEMAC interface 1.
The multicast reject bit provides a means of blocking receive multicast Ethernet frames without needing to clear out
any multicast address values stored in the multicast address table. It also provides a means for allowing more than
4 multicast addresses to be received (the limit of the multicast address table). To accept more than 4 multicast
addresses, the AFM register would be set to promiscuous mode and the multicast reject bit of this register set to
allow multicast frames. Note that software may also need to filter out additional receive frames with other
addresses.
The broadcast reject bit provides the only means for rejecting receive broadcast Ethernet frames.
Due to the design of the TEMAC component, setting the reset bit in either RAF register will reset all (both interfaces)
of the TEMAC component.
As additional functionality was added to the core, this register became the convenient home for new bits to control
those new functions. Care has been take to minimize the effect of these new bits on existing applications by
ensuring that the default values of these bits disable new functionality. This will ensure that when applications do
not use the new bits, the core will operate the way it did previously.
X-Ref Target - Figure 5
Reserved
NewFncEnbl
TxVTagMode
StatsRst
TxVStrpMode
McstRej
18 19 20 21 22 23 24 25 26 27 28 29 30 31
RxVStrpMode
BcstRej
EMultiFltrEnbl
RxVTagMode
HtRst
DS537_05_091909
Figure 5: Reset and Address Filter Registers (offset 0x000 and 0x040)
Table 9 shows the Reset and Address Filter Register bit definitions.
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