DS537 Datasheet, PDF (138/148 Pages) Xilinx, Inc – LogiCORE IP XPS LL TEMAC

LogiCORE IP XPS LL TEMAC (v2.03a)
Gigabit Media Independent Interface (GMII)
The Gigabit Media Independent Interface (GMII), defined in IEEE 802.3 clause 35, is an extension of the MII used to
connect at 1-Gb/S to the PHY devices.
MII can be considered a subset of GMII, and as a result, GMII/MII together can carry Ethernet traffic at 10 Mb/S,
100 Mb/S, and 1 Gb/S.
When the GMII interface is selected with parameters for the XPS_LL_TEMAC, a GMII/MII interface is used which
is capable of all three Ethernet speeds.
Please refer toUG138 LogicCORE IP Tri-Mode Ethernet MAC User Guide for an equivalent diagram of the clock
management scheme.
Soft TEMAC GMII Constraints
Refer to Answer Record 32713 for constraint examples. Refer to UG625 for an overview of the various constraints
used.
Design Implementation
Target Technology
The intended target technology is an FPGA listed in the Supported Device Family field of the LogiCORE IP Facts
table.
Device Utilization and Performance Benchmarks
Because the XPS_LL_TEMAC is a module that will be used with other design pieces in the FPGA, the utilization
and timing numbers reported in this section are just estimates. As the XPS_LL_TEMAC is combined with other
pieces of the FPGA design, the utilization of the FPGA resources and the timing of the XPS_LL_TEMAC design will
vary from the results reported here. The XPS_LL_TEMAC benchmarks for GMII systems are shown in Table 138 for
a Virtex-6 FPGA, in Table 139 for a Virtex-5 FPGA, in Table 140 for a Virtex-4 FPGA, in Table 141 for a Spartan-6
FPGA, and in Table 142 for a Spartan-3 FPGA.
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